Field programmable gate array with internal phase-locked loop

A field programmable gate array system comprising:

• (a) a field programmable gate array comprising:
• (1) a first interface comprising:
• (A) a first reference clock pin, wherein said first reference clock pin is configured to receive a first clock signal having a first frequency and a first phase;
• (B) a second reference clock pin, wherein said second reference clock pin is configured to receive the first clock signal;
• (C) a first plurality of data pins, wherein said first plurality of data pins is configured to receive a first serial data stream;
• (D) a second plurality of data pins, wherein said second plurality of data pins is configured to transmit a second serial data stream;
• (2) a deserializer operationally connected to:
• (A) the first reference clock pin to receive as a first input the first clock signal and
• (B) the first plurality of data pins to receive as a second input the first serial data stream,
• and wherein the deserializer is configured to:
• (A) convert the first serial data stream into a first plurality of parallel data streams having a first amount of data streams, and
• (B) generate a first receiver side clock signal based on the first clock signal, wherein the first receiver side clock signal has a third frequency and a third phase;
• and
• (C) transmit the first plurality of parallel data streams and the first receiver side clock signal within the field programmable gate array;
• (3) computational circuitry operationally connected to the deserializer to receive the first plurality of parallel data streams and the first receiver side clock signal,
• wherein the computational circuitry is configured to perform a first set of operations on the first plurality of parallel data streams to generate a second plurality of parallel processed data streams having a second amount of data streams and the computational circuitry performs the first set of operations to generate the second plurality of parallel processed data without use of a clock domain crossing circuit;
• (4) a serializer operationally connected to:
• (A) an adjustable transceiver phase lock loop to receive as a third input a first wire rate clock signal, wherein the first wire rate clock signal has a fourth frequency and a fourth phase;
• (B) the second plurality of data pins to transmit as a first output the second serial data stream;
• (C) the computational circuitry, wherein the serializer receives the second plurality of parallel processed data streams from the computational circuitry and the serializer transmits to the computational circuitry a first transmitter side clock signal including a fifth frequency and a fifth phase;
• and
• wherein the serializer is configured to:
• (A) convert the second plurality of parallel processed data streams into the second serial data stream;
• (B) generate the first transmitter side clock signal based on the first wire rate signal, wherein the first transmitter side clock signal has the fifth frequency and the fifth phase, wherein the fifth frequency is different than and less than the fourth frequency;
• and
• (C) transmit the second serial data stream to the second plurality of data pins for transmission off the field programmable gate array;
• and
• (b) a phase control circuit, provided at least partially on the field programmable gate array, wherein the phase control circuit comprises:
• (1) a phase detector configured to compare the third phase of the first receiver side clock signal to the fifth phase of the transmitter side clock signal and to generate a phase difference indicator signal based on a difference between the third phase of the first receiver side clock signal and the fifth phase of the transmitter side clock signal;
• (2) a phase controller operationally connected to the phase detector and configured to receive the phase difference indicator signal, and wherein the phase controller is configured to determine adjustment information based on the phase difference indicator signal;
• and
• (3) the adjustable transceiver phase lock loop operationally connected to the phase controller and configured to receive the adjustment information as well as operationally connected to the second reference clock pin of the first interface of the field programmable gate array, wherein the adjustable transceiver phase lock loop is configured to generate a second clock signal including the second frequency and the second phase based on the first clock signal received via the second reference clock pin and process the second clock signal based on the adjustment information received from the phase controller to generate the first wire rate clock signal,
• wherein the transmitter side clock signal and the first receiver side clock signal are phase aligned so that there is a fixed phase difference between the third phase and the fifth phase.