Reducing chip latency at a clock boundary by reference clock phase adjustment

A computer system comprising one or more processors, one or more computer-readable memories, one or more computer-readable storage devices, and program instructions, stored on at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, the stored program instructions comprising:

• program instructions to learn a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of a receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary by:
• program instructions to run a first test line sequence on the data path comprising a plurality of line test cycles;
• program instructions to observe a comparison of data rising output from the buffer on a rising edge of the chip clock compared with an output of a pattern generator in comparison with an expected output;
• in response to the comparison matching the expected output, program instructions to decrement a load to unload delay across the clock boundary by advancing each of an unload pointer for controlling output from the buffer and the pattern generator by two chip clock cycles in one line test cycle of the plurality of line test cycles;
• program instructions to observe the comparison of the data rising output from the buffer on the rising edge of the chip clock compared with the output of the pattern generator in comparison with the expected output program instructions, in response to the comparison not matching the expected output, to increment the load to unload delay by freezing each of the unload pointer and the pattern generator by one chip clock cycle in the one line test cycle;
• and
• program instructions to capture and compare the data rising output from the buffer on the rising edge of the chip clock compared with the data falling output from the buffer on the falling edge of the chip clock;
• and
• program instructions to dynamically adjust a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.

A computer program product comprising one or more computer-readable storage devices and program instructions, stored on at least one of the one or more storage devices, the stored program instructions comprising:

• program instructions to learn a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of a receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary by:
• program instructions to run a first test line sequence on the data path comprising a plurality of line test cycles;
• program instructions to observe a comparison of data rising output from the buffer on a rising edge of the chip clock compared with an output of a pattern generator in comparison with an expected output;
• in response to the comparison matching the expected output, program instructions to decrement a load to unload delay across the clock boundary by advancing each of an unload pointer for controlling output from the buffer and the pattern generator by two chip clock cycles in one line test cycle of the plurality of line test cycles;
• program instructions to observe the comparison of the data rising output from the buffer on the rising edge of the chip clock compared with the output of the pattern generator in comparison with the expected output;
• program instructions, in response to the comparison not matching the expected output, to increment the load to unload delay by freezing each of the unload pointer and the pattern generator by one chip clock cycle in the one line test cycle;
• and
• program instructions to capture and compare the data rising output from the buffer on the rising edge of the chip clock compared with the data falling output from the buffer on the falling edge of the chip clock;
• and
• program instructions to dynamically adjust a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.