System and method for hitless clock switching

A system for hitless clock switching, comprising a sampling circuitry group, a phase detector group, a compensator group, a signal selector and a phase-locked loop that are sequentially connected, wherein

• the sampling circuitry group is configured to sample at least one set of reference clock signals to correspondingly obtain at least one set of sampling information and send the at least one set of sampling information to the phase detector group, wherein each set of reference clock signals comprises a primary reference clock signal and a secondary reference clock signal, primary reference clock signals in different sets of reference clock signals are the same, secondary reference clock signals in different sets of reference clock signals are different, and each set of sampling information comprises first sampling information corresponding to the primary reference clock signal and second sampling information corresponding to the secondary reference clock signal;
• the phase detector group comprises at least one phase detector, wherein each phase detector receives a set of sampling information and processes the set of sampling information as received to obtain a phase difference, and sends the phase difference and the secondary reference clock signal to the compensator group;
• the compensator group is configured to add the phase difference sent by each phase detector and a phase of the secondary reference clock signal sent by the same phase detector to obtain a backup reference clock signal, and send the backup reference clock signal to the signal selector, wherein the compensator group comprises at least one compensator;
• the signal selector is configured to receive the primary reference clock signal and at least one backup reference clock signal sent by the compensator group, determine the primary reference clock signal as received as a target reference clock signal in a case that the primary reference clock signal is normal, determine one of the at least one backup reference clock signal as the target reference clock signal in a case that the primary reference clock signal is abnormal or missing, and send the target reference clock signal as determined to the phase-locked loop;
• and
• the phase-locked loop is configured to perform loop control on the target reference clock signal as received.