Configurable first in first out and deserializer circuitry
AssigneeIntel Corporation
InventorsEah Loon Alan Chuah, Hui Hui Ngu
Life of this patent
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Abstract
An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites, such as by filling via opening and/or using jumpers, may form a deserializer circuit with a first via configuration or a first-in first-out (FIFO) circuit with a second via configuration.
Claims20
An integrated circuit device comprising:
- a data interface block;
- a plurality of data logic blocks connected to the data interface block at least in part by vias of a via layer, wherein the vias are arranged on the via layer in a via configuration;
- and
- the via layer, wherein the via layer causes the data interface block and the plurality of data logic blocks to operate at least in part as a deserializer circuit when the via configuration of the via layer is a first via configuration and a first-in-first-out (FIFO) circuit when the via configuration of the via layer is a second via configuration.
A method of manufacturing an integrated circuit comprising:
- forming circuitry using a first one or more masks;
- and
- forming vias using a second one or more masks to produce one of a plurality of via configurations, wherein a first via configuration of the plurality of via configurations causes a first portion of the circuitry to operate as a deserializer circuit, and wherein a second via configuration of the plurality of via configurations causes a second portion of the circuitry to operate as a first-in-first-out (FIFO) circuit.
A configurable circuit, comprising:
- a circuit comprising one or more data logic blocks comprising one or more flip-flops, one or more multiplexers, one or more inverters, one or more comparators, one or more read address counters, one or more read address decoders, one or more write address counters, one or more write address decoders, or a combination thereof;
- and
- a plurality of vias connected to at least a portion of the circuit to implement a first-in-first-out circuit in a first via configuration or a deserializer circuit in a second via configuration.
Dependencies are inferred from the claim text.