Digital average current-mode control voltage regulator and a method for tuning compensation coefficients thereof

A digital controller for controlling average-current-mode voltage regulator having an output connected to a load and an auto-tuning capability, said controller comprising:

• a) a digital voltage-sampling window analog-to-digital converter (ADC), based on delay-lines (DLs) and configured to obtain a sample of the difference between the reference voltage and the output voltage (voltage error signal), and to convert said voltage error signal from analog to digital representation;
• b) a digital current-sampling window ADC, based on DLs and configured to obtain a sample of the inductor current and to converter said inductor current from analog to digital representation;
• c) a digital voltage-loop compensator receiving as input the digital voltage error signal, configured to generate a current reference signal based thereupon;
• d) a digital current-loop compensator receiving as inputs the inductor current signal and the current reference signal, configured to generate a duty-ratio command signal based thereupon;
• and
• e) a digital hybrid high resolution (HR) digital pulse width modulator (DPWM) receiving as input the duty-ratio command signal and generating a pulse-width-modulated signal that is fed to the gates of the converter's transistors to thereby control the current and voltage supplied to said load,
• wherein said digital voltage-loop compensator and said digital current-loop compensator are auto-tuned according to an auto-tuning process that comprises the following steps:
• f) defining a default set of coefficients either according to an initial specification of the output target voltage or to satisfy stability of the controller and its output with a low bandwidth, derived as a fraction of switching frequency;
• g) loading said default set of coefficients to each compensator;
• h) extracting coefficients for the digital current-loop compensator from the output current;
• i) driving a small current step from said current-loop compensator to the voltage output and perturbing its voltage;
• and
• j) estimating, from the output capacitor's capacitance, data required to set coefficients of said digital voltage-loop compensator;
• wherein the digital voltage-sampling window ADC and the digital current-sampling window ADC are a single digital window ADC based on DLs, said single digital window ADC further comprises:
• k) an input multiplexer (MUX) and an output de-multiplexer for switching between voltage and current sampling.