Space efficient and power spike resistant ESD power clamp with digitally timed latch

A power clamp apparatus for protecting a circuit, comprising:

• a trigger circuit comprising an RC network and an inverter stage circuit;
• a clamp transistor coupled to the trigger circuit;
• a timing circuit coupled to the trigger circuit and a timing controlled transistor, wherein the timing circuit comprises an oscillator circuit and a divider circuit, wherein the oscillator circuit provides an input to the divider circuit and the divider circuit being connected to the timing controlled transistor;
• and
• the timing controlled transistor further being coupled to the trigger circuit and the timing circuit.

A method for protecting a circuit using a power clamp device, comprising:

• detecting an electrostatic discharge (ESD) event by a trigger circuit, wherein the trigger circuit includes an RC network and an inverter stage circuit;
• providing, by the trigger circuit, a trigger signal to activate a clamp transistor;
• and
• generating, by a timing circuit, a timing signal to control a timing controlled transistor, wherein the timing circuit comprises an oscillator circuit and a divider circuit.