CHIP package
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Kuo-Chung Yee
Life of this patent
Estimating the term…
Abstract
An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.
Claims20
A chip package, comprising:
- an integrated circuit chip comprising an active surface;
- a plurality of memory chips stacked on the active surface of the integrated circuit chip and electrically connected to the integrated circuit chip;
- an insulating encapsulation, laterally encapsulating the plurality of memory chips and partially covering the active surface of the integrated circuit chip;
- and
- a redistribution circuit structure disposed on the plurality of memory chips and the insulating encapsulation, the redistribution circuit structure being electrically connected to the integrated circuit chip and the plurality of memory chips, wherein the active surface of the integrated circuit chip faces the plurality of memory chips.
A chip package, comprising:
- an integrated circuit chip comprising an active surface and a rear surface opposite to the active surface, wherein the integrated circuit chip is encapsulated by a first insulating portion;
- a plurality of memory chips stacked on the active surface of the integrated circuit chip and the first insulating portion, wherein the plurality of memory chips are electrically connected to the integrated circuit chip, the plurality of memory chips are encapsulated by a second insulating portion;
- and
- a redistribution circuit structure disposed on the rear surface of the integrated circuit chip and the first insulating portion, the redistribution circuit structure being electrically connected to the integrated circuit chip and the plurality of memory chips, wherein the rear surface of the integrated circuit chip faces the redistribution circuit structure.
A chip package, comprising:
- an integrated circuit chip comprising an active surface and a rear surface opposite to the active surface, wherein the integrated circuit chip is encapsulated by a first insulating portion;
- a plurality of memory chips stacked on the rear surface of the integrated circuit chip and the first insulating portion, wherein the plurality of memory chips are electrically connected to the integrated circuit chip, the plurality of memory chips are encapsulated by a second insulating portion;
- and
- a redistribution circuit structure disposed on the active surface of the integrated circuit chip and the first insulating portion, the redistribution circuit structure being electrically connected to the integrated circuit chip and the plurality of memory chips, wherein the active surface of the integrated circuit chip faces the redistribution circuit structure.
Dependencies are inferred from the claim text.