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US 10,770,598 B2Granted
Memory devices and methods of manufacture thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsAlexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
Life of this patent
Estimating the term…
Abstract
Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.
Claims20
A method of manufacturing a memory device, the method comprising:
- forming a first patterned mask over a substrate;
- patterning the substrate to form a first recess and a second recess using the first patterned mask as a mask;
- filling the first recess and the second recess with a dielectric material to form a first isolation region and a second isolation region, the first isolation region being interposed between a first region of the substrate and a second region of the substrate, the second isolation region interposed between the second region and a third region of the substrate;
- forming a second patterned mask over the substrate;
- patterning the substrate to form a third recess using the second patterned mask as a mask, wherein the third recess is in the first region;
- forming a dielectric layer over the first region, the second region, and the third region of the substrate, the dielectric layer extending into the third recess;
- and
- forming a conductive electrode over the dielectric layer in the first region, the second region, and the third region of the substrate, wherein the conductive electrode comprises a plate of a first capacitor in the first region, a gate of a transistor in the second region, and a plate of a second capacitor in the third region.
5 more elements
A method of manufacturing a memory device, the method comprising:
- patterning a substrate to form a first recess, a second recess, and third recess using one or more patterned masks;
- filling the first recess, the second recess, and the third recess with a first dielectric material, the first dielectric material in the first recess forming a first isolation region, the first dielectric material in the second recess forming a second isolation region, the first isolation region being interposed between a first region of the substrate and a second region of the substrate, the second isolation region interposed between the second region and a third region of the substrate, wherein the third recess is in the first region;
- removing the first dielectric material in the third recess;
- doping the substrate along sidewalls of the third recess;
- forming source/drain regions in the second region;
- forming a dielectric layer over the first region, the second region, and the third region;
- and
- forming a conductive layer over the dielectric layer in the first region, the second region, and the third region of the substrate, wherein the conductive layer comprises a plate of a first capacitor in the first region, a gate of a transistor in the second region, and a plate of a second capacitor in the third region.
5 more elements
A method of manufacturing a memory device, the method comprising:
- forming a first isolation region and a second isolation region in a substrate, the first isolation region being interposed between a first region of the substrate and a second region of the substrate, the second isolation region interposed between the second region and a third region of the substrate;
- forming a patterned mask over the substrate;
- patterning the substrate to form a recess using the patterned mask as a mask, wherein the recess is in the first region;
- forming a dielectric layer over the first region, the second region, and the third region of the substrate, the dielectric layer extending into the recess;
- and
- forming a conductive electrode over the dielectric layer in the first region, the second region, and the third region of the substrate, wherein the conductive electrode comprises a plate of a first capacitor in the first region, a gate of a transistor in the second region, and a plate of a second capacitor in the third region.
3 more elements
Dependencies are inferred from the claim text.