Fin field effect transistor including a single diffusion break with a multi-layer dummy gate
AssigneeInternational Business Machines Corporation
InventorKangguo Cheng
Life of this patent
Estimating the term…
Abstract
In one example, a fin field effect transistor including a single diffusion break with a multi-layer dummy gate is disclosed. One example of field effect transistor includes a first transistor array comprising a first active gate, a second transistor array comprising a second active gate, and a single diffusion break formed between the first transistor array and the second transistor array, wherein the single diffusion break comprises a dummy gate comprising multiple layers of different materials.
Claims19
A field effect transistor, comprising:
- a first transistor array comprising a first active gate;
- a second transistor array comprising a second active gate;
- and
- a single diffusion break formed between the first transistor array and the second transistor array, wherein the single diffusion break comprises a dummy gate comprising a layer of dielectric material, and an inactive gate structure formed over the layer of dielectric material, wherein a lateral width of the layer of dielectric material is substantially equal to a lateral width of the inactive gate structure,
- wherein a sidewall spacer directly contacts and separates the layer of dielectric material from an adjacent epitaxial source drain region.
A field effect transistor, comprising:
- a substrate;
- a first transistor array formed on the substrate, comprising:
- a first channel formed as a first fin;
- a first active gate wrapping around the first fin;
- a second transistor array formed on the substrate, comprising:
- a second channel formed as a second fin;
- a second active gate wrapping around the second fin;
- and
- a single diffusion break formed between the first transistor array and the second transistor array, the single diffusion break comprising:
- a layer of dielectric material, wherein a top surface of the layer of the dielectric material sits higher than top surfaces of the first fin and the second fin;
- and
- an inactive gate formed over the layer of dielectric material, wherein the inactive gate, the first active gate, and the second active gate are formed from identical materials,
- wherein a lateral width of the layer of dielectric material is substantially equal to a lateral width of the inactive gate,
- wherein upper most surfaces of both the layer of dielectric material and adjacent epitaxial source drain regions are above a lower most surface of a sidewall spacer separating the layer of dielectric material from the adjacent epitaxial source drain regions.
A semiconductor structure comprising:
- a first array of fins and a second array of fins on a substrate;
- an array of gate structures perpendicular to and wrapping portions of both the first array of fins and the second array of fins;
- and
- a single dielectric material directly below one gate structure, the single dielectric material isolates the first array of fins from the second array of fins, wherein sidewalls of the single dielectric material are coplanar with sidewalls of the one gate structure.
Dependencies are inferred from the claim text.