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US 10,770,588 B2Granted
(110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChao-Ching Cheng, Chih-Hsin Ko, Hsingjen Wann
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Abstract
A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.
Claims20
A device comprising:
- a fin structure extending from a semiconductor substrate, wherein the fin structure has a top surface having a (100) crystallographic orientation and sidewall surfaces having a (110) crystallographic orientation, the sidewall surfaces having the (110) crystallographic orientation extending to a top surface of the semiconductor substrate having a (100) crystallographic orientation;
- a gate structure traversing the fin structure, the gate structure traversing a source region and a drain region of the fin structure such that a channel region is defined between the source region and the drain region;
- and
- a hard mask layer disposed in the channel region over the top surface of the fin structure having the (100) crystallographic orientation,
- wherein the gate structure includes a gate dielectric, a gate electrode, and a sidewall spacer disposed alongside the gate dielectric and the gate electrode, the gate dielectric being disposed over the hard mask layer and the sidewall surfaces of the fin structure having the (110) crystallographic orientation, and the gate electrode being disposed over the gate dielectric, wherein the sidewall spacer is disposed on and covers a vertical side surface of the hard mask layer, wherein the fin structure includes a III-V semiconductor material.
2 more elements
A device comprising:
- a fin structure extending over a semiconductor substrate, wherein the fin structure has a first sidewall surface, a second sidewall surface, and a top surface extending from the first sidewall surface to the second sidewall surface, the top surface facing away from the semiconductor substrate, the first sidewall surface having a (110) crystallographic orientation extending to a top surface of the semiconductor substrate having a (100) crystallographic orientation,
- the top surface of the fin structure having the (100) crystallographic orientation;
- and
- a gate structure traversing the fin structure, wherein the gate structure includes:
- a hard mask layer disposed on the top surface of the fin structure;
- a gate dielectric disposed over the hard mask layer;
- a gate electrode disposed over the gate dielectric;
- and
- a sidewall spacer disposed alongside the hard mask layer, the gate dielectric, and the gate electrode, wherein the sidewall spacer covers a side surface of the hard mask layer, wherein the fin structure includes a III-V semiconductor material.
6 more elements
A device comprising:
- a semiconductor fin structure extending over a semiconductor substrate, wherein the semiconductor fin structure has a first sidewall surface and an opposing second sidewall surface and a top surface extending between the first sidewall surface and the second sidewall surface, the first sidewall surface having a (110) crystallographic orientation extending to a top surface of the semiconductor substrate having a (100) crystallographic orientation;
- a dielectric isolation structure embedded within the semiconductor substrate surrounding the semiconductor fin structure;
- a hard mask layer disposed over the top surface of the semiconductor fin structure;
- a gate dielectric disposed over and physically contacting the hard mask layer;
- a gate electrode disposed over the gate dielectric;
- and
- a sidewall spacer disposed alongside the hard mask layer, the gate dielectric, and the gate electrode, wherein the sidewall spacer covers a side surface of the hard mask layer, wherein the semiconductor fin structure includes a III-V semiconductor material.
4 more elements
Dependencies are inferred from the claim text.