Self-aligned buried contact for vertical field-effect transistor and method of production thereof

A device comprising:

• first and second high-k/metal gate (HKMG) structures over a first portion of a silicon (Si) substrate, and a third HKMG structure over a second portion of the Si substrate;
• an inter-layer dielectric (ILD) over a portion of the Si substrate and on sidewalls of the first, second and third HKMG structures;
• a spacer liner on sidewalls of the ILD between the second and third HKMG structures;
• and
• a buried contact layer between the spacer liner and in a portion of the Si substrate,
• wherein the spacer liner comprises a top surface, a first surface and a second side surface, wherein the top surface of the spacer liner is in direct contact with the ILD, wherein a portion of the first surface of the spacer liner is in direct contact with the ILD, and wherein a portion of the second surface of the spacer liner is in direct contact with the buried contact layer, and
• wherein the first, second and third HKMG structures comprise:
• a high-k (HK) layer on sidewall portions of first, second and third fin structures;
• a work function metal (WFM) layer over the HK layer;
• a first spacer over the HK layer and the WFM layer and on sidewall portions of the first, second and third fin structures;
• a second spacer over the first spacer;
• and
• a top source/drain (S/D) regions over the first, second and third HKMG structures and between the first spacer.