Vertical group III-N devices and their methods of fabrication

A semiconductor structure, comprising:

• a doped buffer layer above a substrate;
• a group III-N semiconductor material disposed on the doped buffer layer, the group III-N semiconductor material having a pair of sloped sidewalls and a planar uppermost surface;
• a first and a second drain region disposed on the substrate separated by the doped buffer layer;
• an insulator layer disposed on the first and the second drain regions;
• a polarization charge inducing layer disposed on and conformal with the group III-N semiconductor material, the polarization charge inducing layer having a first portion disposed on the sloped sidewalls of the group III-N semiconductor material and a second portion disposed on the planar uppermost surface of the group III-N semiconductor material, wherein the first portion has a thickness and the second portion has a thickness greater than the thickness of the first portion;
• a first gate and a second gate structure disposed on the first portion of the polarization charge inducing layer, the first and the second gate structures separated by the group III-N semiconductor material;
• and
• a source region disposed on the second portion of the polarization charge inducing layer.

A method of fabricating a group III-nitride (III-N) transistor, the method comprising:

• forming a material layer stack on a substrate, the material layer stack comprising a metal layer and an insulator layer on the metal layer;
• forming a trench in the material layer stack;
• forming a doped buffer layer in the trench;
• forming a group III-N semiconductor material in the trench and on the doped buffer layer, wherein the group III-N material has sidewalls and an uppermost surface;
• forming a polarization charge inducing layer on the sidewalls and on the uppermost surface of the group III-N semiconductor material;
• where the portion of the polarization charge inducing layer formed on the sidewall of the group III-N semiconductor material has a thickness less than a thickness of the portion of the polarization charge inducing layer on the uppermost surface of the group III-N semiconductor material;
• forming a dielectric hardmask layer on an uppermost surface of the polarization charge inducing layer and on a portion of a sidewall surface of the polarization charge inducing layer;
• forming a gate stack on the polarization charge inducing layer on the sidewall of the polarization charge inducing layer, and on the hardmask layer;
• forming a dielectric layer on the gate stack, on the insulator layer planarizing to expose the hardmask layer;
• forming a source contact on an uppermost surface of the polarization charge inducing layer.