Memory structure and manufacturing method thereof
AssigneeUnited Microelectronics Corp.
InventorsHsueh-Chun Hsiao, Tzu-Yun Chang, Chuan-Fu Wang, Yu-Huang Yeh
Life of this patent
Estimating the term…
Loading patent…
AssigneeUnited Microelectronics Corp.
InventorsHsueh-Chun Hsiao, Tzu-Yun Chang, Chuan-Fu Wang, Yu-Huang Yeh
Estimating the term…
A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.
A memory structure, comprising:
A method of manufacturing a memory structure, comprising:
Dependencies are inferred from the claim text.