Interlayer dielectric replacement techniques with protection for source/drain contacts

A method for fabricating a semiconductor IC device, comprising:

• forming a field-effect transistor device on a semiconductor substrate, wherein the field-effect transistor device comprises a gate structure and source/drain layers;
• forming a sacrificial interlayer dielectric layer to encapsulate the field-effect transistor device;
• performing a metallization process to form metallic source/drain contacts in the sacrificial interlayer dielectric layer in contact with source/drain layers of the field-effect transistor device;
• depositing a semiconductor layer on the sacrificial interlayer dielectric layer and the metallic source/drain contacts;
• performing a thermal anneal process to induce a reaction between the semiconductor layer and the metallic source-drain contacts to form metal-semiconductor alloy capping layers in upper surface regions of the metallic source/drain contacts;
• removing unreacted portions of the semiconductor layer remaining after the thermal anneal process;
• performing an etch process to remove the sacrificial interlayer dielectric layer, wherein the etch process is selective to the metal-semiconductor alloy capping layers such that the metal-semiconductor alloy capping layers protect the metallic source/drain contacts from etch damage during the etch process;
• and
• forming a low-k interlayer dielectric layer in place of the removed sacrificial interlayer dielectric layer.