Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses

A circuit, comprising:

• a semiconductor substrate;
• an insulating region delimiting an active region of the semiconductor substrate;
• at least one component unfavorably sensitive to compressive stress at least partially in the active region, wherein the at least one component unfavorably sensitive to compressive stress is an NMOS transistor belonging to a control unit of a memory plane of an integrated memory device, the memory plane having nonvolatile memory cells and selection transistors with buried gates formed in trenches;
• at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region;
• wherein the at least one electrically inactive trench and the trenches for the buried gates have a same depth within the semiconductor substrate.