Small-gap coplanar tunable capacitors and methods for manufacturing thereof

A method for fabricating a coplanar capacitor, the method comprising:

• depositing a metal layer on a voltage-tunable dielectric layer;
• depositing an inter-level dielectric layer on the metal layer;
• etching first material from the inter-level dielectric layer and second material from the metal layer to form a plurality of bias lines covered at least partially by respective portions of the inter-level dielectric layer;
• depositing an oxide layer on exposed surface portions of the inter-level dielectric layer and on exposed surface portions of the voltage-tunable dielectric layer, wherein the oxide layer that is deposited includes upright portions between the inter-level dielectric layer and the voltage-tunable dielectric layer;
• etching third material from the oxide layer to expose portions of the inter-level dielectric layer, to expose portions of the voltage-tunable dielectric layer and to form, from the upright portions, a plurality of sidewall spacers, wherein each of the plurality of sidewall spacers is located adjacent one of the plurality of bias lines, and wherein the etching of the third material from the oxide layer results in exposed portions of the inter-level dielectric layer and exposed portions of the voltage-tunable dielectric layer;
• depositing a metallization layer on the exposed portions of the inter-level dielectric layer and on the exposed portions of the voltage-tunable dielectric layer;
• and
• etching fourth material from the metallization layer to form a plurality of RF electrodes, the metallization layer further forming a DC bias pad, an input pad, an output pad, or any combination thereof.

A method for fabricating a coplanar capacitor, the method comprising:

• depositing a voltage-tunable dielectric layer on a substrate;
• depositing a metal layer on the voltage-tunable dielectric layer;
• depositing an inter-level dielectric layer on the metal layer;
• etching first material from the inter-level dielectric layer and second material from the metal layer to form a plurality of bias lines covered at least partially by respective portions of the inter-level dielectric layer;
• depositing an oxide layer on exposed surface portions of the inter-level dielectric layer and on exposed surface portions of the voltage-tunable dielectric layer, wherein the oxide layer that is deposited includes upright portions between the inter-level dielectric layer and the voltage-tunable dielectric layer;
• etching third material from the oxide layer to expose portions of the inter-level dielectric layer, to expose portions of the voltage-tunable dielectric layer and to form, from the upright portions, a plurality of sidewall spacers, wherein each of the plurality of sidewall spacers is located adjacent one of the plurality of bias lines, and wherein the etching of the third material from the oxide layer results in exposed portions of the inter-level dielectric layer and exposed portions of the voltage-tunable dielectric layer;
• and
• etching fourth material from a metallization layer that had been deposited on the exposed portions of the inter-level dielectric layer and on the exposed portions of the voltage-tunable dielectric layer, the etching of the fourth material from the metallization layer forming a plurality of RF electrodes, the metallization layer further forming an interconnect between a resistive layer and one of the plurality of bias lines.