Method for manufacturing LTPS type TFT
AssigneeWuhan China Star Optoelectronics Technology Co., Ltd.
InventorsJuncheng Xiao, Chao Tian
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Abstract
The present disclosure provides an LTPS type TFT and a method for manufacturing the same. The TFT includes a first contact hole and a second contact hole, where the first contact hole and the second contact hole pass through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that a portion of the heavily doped area is exposed. In addition, a transparent electrode is electrically connected to the source/drain electrode or the second gate electrode and a portion of the heavily doped area.
Claims12
A method for manufacturing a low temperature poly silicon (LTPS) type thin film transistor (TFT), comprising steps of:
- providing a substrate, and forming a silicon channel layer on the substrate;
- forming a first insulating layer on the silicon channel layer;
- forming a first gate electrode of the TFT on the first insulating layer;
- performing an ion implantation on a portion of the silicon channel layer to form a doped area, wherein the doped area includes a lightly doped area and a heavily doped area, and the heavily doped area includes a first heavily doped area and a second heavily doped area;
- forming a second insulating layer, a source/drain electrode, and a third insulating layer on the first gate electrode in sequence;
- forming a first contact hole on the LTPS type TFT, wherein the first contact hole exposes a portion of the source/drain electrode and a portion of the first heavily doped area;
- and
- forming a first transparent electrode on the third insulating layer, wherein the first transparent electrode is electrically connected to the portion of the source/drain electrode and the portion of the first heavily doped area via the first contact hole.
A method for manufacturing a low temperature poly silicon (LTPS) type thin film transistor (TFT), comprising steps of:
- providing a substrate and forming a silicon channel layer on the substrate;
- forming a first insulating layer on the silicon channel layer;
- forming a first gate electrode of the TFT on the first insulating layer;
- performing an ion implantation on a portion of the silicon channel layer to form a doped area, and wherein the doped area includes a first doped area and a second doped area;
- forming a second insulating layer, a source/drain electrode, and a third insulating layer on the first gate electrode in sequence;
- forming a first contact hole on the LTPS type TFT, wherein the first contact hole exposes a portion of the source/drain electrode and a portion of the first doped area;
- and
- forming a first transparent electrode on the third insulating layer, wherein the first transparent electrode is electrically connected to the portion of the source/drain electrode and the portion of the first doped area via the first contact hole.
Dependencies are inferred from the claim text.