Systems, methods, and apparatus for enabling high voltage circuits

A silicon on insulator structure comprising:

• a high resistivity silicon substrate configured to be coupled to a reference potential;
• a buried oxide layer overlying the high resistivity silicon substrate;
• a thin silicon layer overlying the buried oxide layer;
• a first circuit formed in a first silicon region of the thin silicon layer, the first circuit configured to be coupled to a first potential, the first silicon region forming a first capacitive coupling between the thin silicon layer and the substrate;
• a second circuit formed in a second silicon region of the thin silicon layer, the second circuit configured to be coupled to a second potential different from the first potential, the second silicon region forming a second capacitive coupling between the thin silicon layer and the substrate;
• and
• a control structure formed in one or more of the substrate, the buried oxide layer and the thin silicon layer, configured to affect a ratio between values of the first and second capacitive couplings,
• wherein:
• a potential difference between a high level of the first potential and the reference potential is equal to or larger than 10 V, and a potential difference between high level of the second potential and the reference potential is equal to or smaller than 3 V,
• the control structure is configured to control one or both of:
• a) a surface potential at a first region of the substrate proximate the first silicon region, and
• b) a surface potential at a second region of the substrate proximate the second silicon region.

A method for reducing a back gate effect in a silicon on insulator structure, the method comprising:

• forming a first silicon region in a thin silicon layer of the silicon on insulator structure, the first silicon region configured to be coupled to a first voltage having a high level equal to or higher than 10 V, the first silicon region forming a first capacitive coupling between the thin silicon layer and a silicon substrate of the silicon on insulator structure;
• forming a second silicon region, isolated from the first silicon region, in the thin silicon layer, the second silicon region configured to be coupled to a second voltage having a high level equal to or lower than 3 V, the second silicon region forming a second capacitive coupling between the thin silicon layer and the substrate;
• forming a control structure configured to affect a ratio between values of the first and the second capacitive couplings;
• coupling the first voltage to the first silicon region and the second voltage to the second silicon region;
• coupling the substrate to a reference potential;
• based on the forming and the coupling, controlling one or both of:
• i) a surface potential at a first region of the substrate proximate the first silicon region, and
• ii) a surface potential at a second region of the substrate proximate the second silicon region, and
• based on the controlling, reducing the back gate effect in one or both of the first silicon region and the second silicon region,
• wherein the substrate is a high resistivity silicon substrate.

A method for reducing a back gate effect in a silicon on insulator structure, the method comprising:

• forming a first silicon region in a thin silicon layer of the structure, the first silicon region configured to be coupled to a first voltage having a high level equal to or higher than 10 V;
• forming a second silicon region, isolated from the first silicon region, in the thin silicon layer, the second silicon region configured to be coupled to a second voltage having a high level equal to or lower than 5 V;
• forming a control structure configured to affect a coupling between the thin silicon layer and a silicon substrate of the structure;
• coupling the first voltage to the first silicon region and the second voltage to the second silicon region;
• coupling the substrate to a reference potential;
• based on the forming and the coupling, controlling one or both of:
• iii) a potential at a first surface region of the substrate proximate the first silicon region, and
• iv) a potential at a second surface region of the substrate proximate the second silicon region, and
• based on the controlling, reducing the back gate effect in one or both of the first silicon region and the second silicon region,
• wherein the substrate is a high resistivity silicon substrate,
• wherein the first and second voltages are DC or switching voltages,
• wherein the control structure resistively couples, through the buried oxide layer, a local silicon region of one of the first silicon region and the second silicon region to the substrate by way of a non-ohmic contact between a through buried oxide layer contact and the high resistivity silicon substrate, and
• wherein the control structure controls the potential at the first/second surface regions during a steady state of the first voltage through a combination of the resistive coupling with a plurality of elemental resistance paths of the high resistivity silicon substrate.