Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area, a logic circuit formed in a peripheral area and a ring structure area separating the memory cell area and the peripheral area, the method comprising:

• forming a memory cell structure;
• forming a protrusion of a substrate in the ring structure area, which protrudes from isolation insulating layers;
• forming a high-k dielectric film in the ring structure area, thereby covering the protrusion and the isolation insulating layers, and in the peripheral area;
• forming a poly silicon film over the high-k dielectric film;
• patterning the poly silicon film and the high-k dielectric film, thereby forming a gate structure in the peripheral area, and a ring structure in the ring structure area;
• and
• forming insulating sidewall spacers on opposing sides of the gate structure in the peripheral area and sides of the ring structure,
• wherein in the ring structure area, the patterned high-k dielectric layer is sealed by the patterned polysilicon layer and the insulating spacers.

A method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area, a logic circuit formed in a peripheral area and a ring structure area separating the memory cell area and the peripheral area, the method comprising:

• forming shallow trench isolations defining the ring structure area;
• protecting the logic circuit area and the ring structure area by a cover layer;
• forming a memory cell structure;
• removing the cover layer;
• forming a protrusion of a substrate in the ring structure area, which protrudes from isolation insulating layers;
• forming a high-k dielectric film in the ring structure area, thereby covering the protrusion and the isolation insulating layers, and in the peripheral area;
• forming a poly silicon film over the high-k dielectric film;
• patterning the poly silicon film and the high-k dielectric film, thereby forming a gate structure in the peripheral area, and a ring structure in the ring structure area;
• and
• forming insulating sidewall spacers on opposing sides of the gate structure in the peripheral area and sides of the ring structure,
• wherein in the ring structure area, the patterned high-k dielectric layer is sealed by the patterned polysilicon layer and the insulating spacers.