Method used in forming integrated circuitry

A method used in forming integrated circuitry, comprising:

• forming a substrate comprising conductive line structures individually comprising opposing longitudinal sides individually comprising sacrificial material that is laterally between insulator material, the sacrificial material comprising metal oxide;
• forming conductive vias laterally between and spaced longitudinally along the conductive line structures;
• forming conductive material directly above and directly against the conductive vias and directly above the conductive line structures;
• etching through the conductive material to the conductive line structures to expose the sacrificial material;
• removing at least some of the sacrificial material to form an upwardly-open void space laterally between the insulator material on the opposing longitudinal sides of individual of the conductive line structures;
• and
• covering the void space with insulating material to leave a sealed void space beneath the insulating material on the opposing longitudinal sides of the individual conductive line structures.

A method used in forming memory circuitry, comprising:

• forming transistors individually comprising:
• a pair of source/drain regions;
• a channel region between the pair of source/drain regions;
• a conductive gate operatively proximate the channel region;
• and
• a gate insulator between the conductive gate and the channel region;
• forming digitline structures that are individually directly electrically coupled to one of the source/drain regions of multiple of the individual pairs of source/drain regions, the digitline structures individually comprising opposing longitudinal sides individually comprising a sacrificial material that is laterally between insulator material, the sacrificial material comprising metal oxide;
• forming conductive vias laterally between and spaced longitudinally along the digitline structures, individual of the conductive vias being directly electrically coupled to one of the other source/drain regions in the individual pairs of source/drain regions;
• forming conductive material of a redistribution layer directly above and directly against the conductive vias and directly above the digitline structures;
• etching through the conductive material to the digitline structures to expose the sacrificial material and to pattern the redistribution layer into separated islands that are individually directly electrically coupled to the individual conductive vias;
• removing at least some of the sacrificial material to form an upwardly-open void space laterally between the insulator material on the opposing longitudinal sides of individual of the digitline structures;
• covering the void space with insulating material to leave a sealed void space beneath the insulating material on the opposing longitudinal sides of the individual digitline line structures;
• and
• forming a plurality of a storage elements that are individually directly electrically coupled to individual of the islands.

A method used in forming integrated circuitry, comprising:

• forming a sacrificial material that is laterally between insulator material, the sacrificial material comprising metal oxide;
• removing at least some of the sacrificial material to form an upwardly-open void space laterally between the insulator material;
• and
• covering the void space with insulating material to leave a sealed void space beneath the insulating material.