Vertical field-effect transistors for monolithic three-dimensional semiconductor integrated circuit devices

A method, comprising:

• forming an etch stop layer on a first substrate;
• forming a first semiconductor layer on the etch stop layer;
• forming an insulating layer on the first semiconductor layer;
• forming a second semiconductor layer on the insulating layer;
• patterning the first semiconductor layer, the insulating layer, and the second semiconductor layer down to the etch stop layer to thereby form a vertical fin structure comprising a first vertical semiconductor fin, a second vertical semiconductor fin, and a fin insulating spacer disposed between the first and second vertical semiconductor fins;
• forming a sacrificial layer of insulating material on the etch stop layer over the first substrate, wherein the sacrificial layer of insulating material encapsulates the first vertical semiconductor fin of the vertical fin structure;
• forming a capping layer on the sacrificial layer of insulating material;
• and
• forming a first device layer on the capping layer, wherein the first device layer comprises a first vertical field-effect transistor device which comprises the second vertical semiconductor fin of the vertical fin structure.