Nanowire transistor device architectures

An integrated circuit structure including a nanowire transistor device, the integrated circuit structure comprising:

• first and second semiconductor nanowires, each of the first and second semiconductors having a curvilinear cross-section;
• a gate comprising a metal, the gate at least partially surrounding each of the first and second semiconductor nanowires;
• and
• a first dielectric structure surrounding the first semiconductor nanowire, such that the first dielectric structure is at least partially between the first nanowire and the gate;
• and
• a second dielectric structure surrounding the second semiconductor nanowire, such that the second dielectric structure is at least partially between the second nanowire and the gate;
• wherein the first and second dielectric structures are configured such that they are merged with one another, providing a single, continuous dielectric layer shared by the first and second semiconductor nanowires, such that at a point of merging, the first and second dielectric structures collectively have an average thickness of less than twice an average thickness of either the first or second dielectric layer alone at a point without such merging.

An integrated circuit comprising:

• first and second nanowires;
• a gate only partially surrounding each of the first and second nanowires;
• a first dielectric layer and a second dielectric layer between the gate and the first nanowire, such that the first dielectric layer surrounds the first nanowire, and the second dielectric layer surrounds the first dielectric layer;
• and
• a third dielectric layer and a fourth dielectric layer between the gate and the second nanowire, such that the third dielectric layer surrounds the second nanowire, and the fourth dielectric layer surrounds the third dielectric layer;
• wherein the second dielectric layer is in direct contact with the fourth dielectric layer, and the first dielectric layer is not in direct contact with the third dielectric layer.