Integrated standard cell structure

An integrated circuit, comprising:

• a first standard cell having a first gate stack, a second gate stack, a first dielectric gate on a first standard cell boundary, and a second dielectric gate contacting the second gate stack;
• a second standard cell having a third gate stack, a fourth gate stack, a third dielectric gate on a second standard cell boundary, and a fourth dielectric gate contacting the fourth gate stack;
• a first continuous active region extending through the first standard cell and the second standard cell;
• and
• a second continuous active region extending through the first standard cell and the second standard cell, wherein each of the first gate stack, the third gate stack, the first dielectric gate, and the third dielectric gate is extending from the first continuous active region to the second continuous active region.

An integrated circuit, comprising:

• a first standard cell having a first gate stack, and having a first dielectric gate on a first standard cell boundary;
• a second standard cell being adjacent to the first standard cell, having a second gate stack, and having a second dielectric gate on a second standard cell boundary;
• a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate;
• a first continuous active region extending through the first standard cell, the first filler cell and the second standard cell along a first direction;
• and
• a second continuous active region extending through the first standard cell, the first filler cell and the second standard cell along the first direction, wherein each of the first gate stack, the second gate stack, the first dielectric gate and the second dielectric gate is extended from a first continuous active region to a second continuous active region.