Methods of manufacturing semiconductor devices

A method of manufacturing a FinFET structure, the method comprising:

• forming a first masking layer over the FinFET structure, the first masking layer comprising an opening over a first fin of the FinFET structure and a first spacer of the FinFET structure;
• forming a second masking layer over the FinFET structure, the second masking layer having a block blocking a portion of the opening in the first masking layer;
• using the first masking layer and the second masking layer as an etching mask, etching a portion of a dielectric layer of the FinFET structure to form a contact opening, wherein the contact opening has a first edge and a second edge located at opposite sides of the contact opening, and wherein the first edge is defined by an edge of the opening in the first masking layer and the second edge is defined by an edge of the block in the second masking layer;
• and
• forming a contact plug in the contact opening along the first spacer and overlying and contacting a portion of the first fin.

A method of manufacturing a memory cell, the method comprising:

• forming a first masking layer over the memory cell, the first masking layer comprising a first opening over a first half-cell of the memory cell and a second opening over a second half-cell of the memory cell;
• forming a second masking layer over the memory cell, the second masking layer having a block blocking a portion of the first opening and a portion of the second opening;
• using the first masking layer and the second masking layer as an etching mask, performing an etching process to form a first contact opening in the first half-cell and a second contact opening in the second half-cell, wherein each of the first contact opening and the second contact opening has a first edge and a second edge located at opposite sides, wherein the first edge of the first contact opening is defined by an edge of the first opening in the first masking layer and the second edge of the first contact opening is defined by an edge of the block in the second masking layer at an edge an edge of the block in the second masking layer;
• and
• forming a first contact plug in the first contact opening and a second contact plug in the second opening,
• wherein
• the forming each of the first contact opening and the second contact opening exposes a portion of a source/drain region of a transistor of the corresponding half-cell and a portion of a gate spacer of the corresponding half-cell, and
• the forming each of the first contact plug and the second contact plug comprises forming the corresponding contact plug over the exposed portion of the corresponding source/drain region and the exposed portion of the corresponding gate spacer.