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US 10,770,445 B2Granted
Methods of fabricating semiconductor packages including reinforcement top die
AssigneeSK hynix Inc.
InventorKwon Whan Han
Life of this patent
Estimating the term…
Abstract
A method of fabricating semiconductor packages may include forming stack structures on a base die wafer, disposing a top die wafer on the stack structures, and forming a molding layer filling a space between the base die wafer and the top die wafer.
Claims15
A method of fabricating semiconductor packages, the method comprising:
- forming stack structures on a base die wafer;
- disposing a top die wafer on the stack structures;
- and
- forming a molding layer filling a space between the base die wafer and the top die wafer,
- wherein the stack structures are comprised of core dies,
- wherein the base die wafer includes base die regions in which integrated circuits are realized and a peripheral region between the base die regions;
- and
- wherein the stack structures overlap with the base die regions, respectively, in a plan view,
- further comprising removing the peripheral region of the base die wafer, a portion of the molding layer overlapping with the peripheral region, and a portion of the top die wafer overlapping with the peripheral region.
6 more elements
A method of fabricating semiconductor packages, the method comprising:
- forming stack structures on a base die wafer;
- disposing a top die wafer on the stack structures;
- and
- forming a molding layer filling a space between the base die wafer and the top die wafer,
- wherein the stack structures are comprised of core dies,
- wherein the base die wafer includes base die regions in which integrated circuits are realized and a peripheral region between the base die regions;
- wherein the stack structures overlap with the base die regions, respectively, in a plan view,
- wherein the core dies are memory semiconductor dies;
- and
- wherein each of the base die regions is a logic semiconductor die in which a controller device for controlling the memory semiconductor dies is integrated.
7 more elements
A method of fabricating semiconductor packages, the method comprising:
- forming stack structures on a base die wafer;
- disposing a top die wafer having a trench, which is opened toward the base die wafer, on the stack structures;
- and
- forming a molding layer filling a space between the base die wafer and the top die wafer,
- wherein the base die wafer includes base die regions in which integrated circuits are realized and a peripheral region between the base die regions;
- wherein the stack structures overlap with the base die regions, respectively, in a plan view;
- and
- wherein the trench of the top die wafer is disposed to overlap with the peripheral region of the base die wafer.
5 more elements
Dependencies are inferred from the claim text.