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US 10,770,443 B2Granted
Clock architecture in heterogeneous system-in-package
AssigneeIntel Corporation
InventorsKarthik Chandrasekar, Shreepad Panth, Ravi Prakash Gutala
Life of this patent
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Abstract
An integrated circuit device that may include programmable logic fabric disposed on an integrated circuit die and a base die that may include clocking circuitry. Synchronization between logic resources in the programmable logic fabric may be performed using clock signals received from the clocking circuitry. The clocking circuitry in the base die may include phase-locked loops, delay-locked loops, clock trees, and other similar circuitry.
Claims22
An electronic device, comprising:
- a logic die, comprising a plurality of logic elements;
- and
- a base die directly coupled to the logic die via an interface, wherein the base die comprises:
- a phase-locked loop configured to generate a first clock signal;
- phase detection and calibration circuitry coupled to the phase-locked loop, wherein the phase detection and calibration circuitry is configured to:
- receive the first clock signal from the phase-locked loop;
- generate a second clock signal and a third clock signal based on the first clock signal;
- reduce skew between the second clock signal and the third clock signal in the base die;
- provide the second clock signal to a first clock tree;
- and
- provide the third clock signal to a second clock tree;
- the first clock tree configured to transmit the second clock signal to a first logic element of the plurality of logic elements via a first connection of the interface;
- and
- the second clock tree configured to transmit the third clock signal to a second logic element of the plurality of logic elements via a second connection of the interface.
11 more elements
A programmable logic device comprising:
- a plurality of sectors comprising:
- a first sector comprising:
- a first plurality of programmable logic elements;
- and
- a first clock tree;
- and
- a second sector comprising:
- a second plurality of programmable logic elements;
- and
- a second clock tree;
- and
- an interface, wherein the first clock tree is configured to receive a first clock signal from a base die through a first connection of the interface, wherein the second clock tree is configured to receive a second clock signal from the base die through a second connection of the interface, and wherein the base die comprises:
- a phase-locked loop configured to generate a third clock signal;
- phase detection and calibration circuitry coupled to the phase-locked loop, wherein the phase detection and calibration circuitry is configured to:
- receive the third clock signal from the phase-locked loop;
- and
- generate the first clock signal configured to be transmitted to the first clock tree based on the third clock signal and the second clock signal configured to be transmitted to the second clock tree based on the third clock signal;
- and
- reduce skew between the first clock signal and the second clock signal in the base die.
16 more elements
A first integrated circuit comprising:
- a first clock tree and a second clock tree;
- a clock source comprising a phase-locked loop;
- phase detection and calibration circuitry coupled to the phase-locked loop, wherein the phase detection and calibration circuitry is configured to:
- receive a first clock signal from the phase-locked loop;
- generate a second clock signal and a third clock signal based on the first clock signal;
- reduce skew between the second clock signal and the third clock signal in the first integrated circuit;
- provide the second clock signal to the first clock tree;
- and
- provide the third clock signal to the second clock tree;
- and
- a first interface configured to couple to a second integrated circuit, wherein the first interface comprises:
- a first connection configured to transmit the second clock signal from the first clock tree and to the second integrated circuit;
- and
- a second connection configured to transmit the third clock signal from the first clock tree to the second integrated circuit.
11 more elements
Dependencies are inferred from the claim text.