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US 10,770,434 B2Granted
Stair-stacked dice device in a system in package, and methods of making same
AssigneeIntel Corporation
InventorsZhicheng Ding, Bin Liu, Yong She, Aiping Tan, Li Deng
Life of this patent
Estimating the term…
Abstract
A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.
Claims21
A stair-stepped memory module in a system in package comprising:
- a matrix including a landing surface;
- a plurality of memory dice stacked in a stair-step relationship and seated in the matrix, the plurality of memory dice, including a memory first die and a memory subsequent die, the memory first die including an active surface and a backside surface and the memory subsequent die including an active surface and a backside surface, wherein the memory first die includes a vertical first bond wire that extends from the memory first die active surface and breaches the matrix landing surface, and the memory subsequent die includes a vertical subsequent bond wire that extends from the memory subsequent die active surface and breaches the matrix landing surface;
- a processor first die disposed on the memory first die and at least partially seated in the matrix, the processor first die including an active surface and a backside surface, wherein a processor bump array is disposed on the processor first die active surface, and wherein the processor bump array extends at least partially away from the matrix landing surface;
- a spacer disposed on the memory first die, and wherein the spacer is disposed between the processor first die and the memory first die vertical bond wire.
1 more element
A method of testing a system in package, comprising:
- applying a test probe to a bump in a bump array of a processor first die that is seated in a matrix, the matrix including a landing surface, and the matrix also containing a stair-stacked memory module including a memory first die and a memory subsequent die;
- applying a test probe to a first vertical bond wire terminal end that extends above the matrix at the landing surface, wherein memory first die includes an active surface and a backside surface and the memory subsequent die including an active surface and a backside surface, wherein the memory first die includes the vertical first bond wire that extends from the memory first die active surface, and the memory subsequent die includes a subsequent vertical bond wire that extends from the memory subsequent die active surface and breaches the matrix landing surface.
A method of assembling a system in package, comprising:
- assembling a stair-stacked memory module to a processor first die and a spacer;
- assembling a dummy layer above the processor first die and the spacer;
- wirebonding a plurality of memory dice from the stair-stacked memory module wherein at least a one bond wire spans between the memory first die the dummy layer;
- with a matrix material precursor, overmolding the processor first die, the spacer, the dummy layer, and the stair-stacked memory module under conditions to partially encapsulate the bond wire;
- removing the dummy layer;
- removing a portion of the matrix material under conditions to reduce the bond wire to a vertical bond wire and to expose an electrical bump that is part of a bump array on the processor first die.
3 more elements
A computing system including a stair-stepped memory module in a system in package comprising a board, and mounted on the board:
- a matrix including a landing surface;
- a plurality of memory dice stacked in a stair-step relationship and seated in the matrix, the plurality of memory dice, including a memory first die and a memory subsequent die, the memory first die including an active surface and a backside surface and the memory subsequent die including an active surface and a backside surface, wherein the memory first die includes a vertical first bond wire that extends from the memory first die active surface and breaches the matrix landing surface, and the memory subsequent die includes a vertical subsequent bond wire that extends from the memory subsequent die active surface and breaches the matrix landing surface;
- a processor first die disposed on the memory first die and at least partially seated in the matrix, the processor first die including an active surface and a backside surface, wherein a processor bump array is disposed on the processor first die active surface, and wherein the processor bump array extends at least partially away from the matrix landing surface;
- a spacer disposed on the memory first die, and wherein the spacer is disposed between the processor first die and the memory first die vertical bond wire.
1 more element
Dependencies are inferred from the claim text.