US 10,770,429 B2Granted

Microelectronic device stacks having interior window wirebonding

AssigneeIntel Corporation

InventorsMin-Tih Lai, Cory A. Runyan

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Abstract

A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate, wherein a first microelectronic die within the microelectronic die stack includes an opening or “window” formed therethrough. The first microelectronic die may be in electronic communication with a second microelectronic die within microelectronic die stack and/or in electrical communication with a microelectronic substrate upon which the microelectronic die stack may be attached, wherein the electronic communication may be created with a bond wire which extends through the opening or “window” in the first microelectronic die.

Claims15

Dependent claims

A microelectronic package, comprising:

a first microelectronic device having a first surface and an opposing second surface, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface;
a second microelectronic device having a first surface and an opposing second surface, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface, wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extends through the second microelectronic device from the second microelectronic device first surface to the second microelectronic device second surface;
and
at least one bond wire electrically attached to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein the bond wire extends through the at least one second microelectronic device opening;
wherein the at least one bond pad in or on the second microelectronic device first surface comprises a pair of bond pads on opposing sides of the at least one opening, and wherein the pair of bond pads are shorted with a conductive trace extending between the pair of bond pads.

2 more elements

A microelectronic package, comprising:

a first microelectronic device having a first surface and an opposing second surface, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface;
a second microelectronic device having a first surface and an opposing second surface, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface, wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extends through the second microelectronic device from the second microelectronic device first surface to the second microelectronic device second surface;
and
at least one bond wire electrically attached to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein the bond wire extends through the at least one second microelectronic device opening;
wherein the at least one bond pad in or on the first microelectronic device first surface comprises a plurality of bond pads;
wherein the at least one bond pad of the second microelectronic device comprises a plurality of bond pads and wherein the opening through the second microelectronic device comprises a single opening;
and
wherein the at least one bond wire comprises a plurality of bond wires, wherein the plurality of bond wires extend through the single opening to form electrical connections between the plurality of bond pads in or on the first microelectronic device first surface and corresponding bonds pad of the plurality bond pads in or on the second microelectronic device first surface.

5 more elements

A The method of forming a microelectronic package, comprising:

forming a first microelectronic device having a first surface and an opposing second surface, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface;
forming a second microelectronic device having a first surface and an opposing second surface, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface, wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extending through the second microelectronic device from the second microelectronic device first surface to the second microelectronic device second surface;
and
electrically attaching at least one bond wire to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein the bond wire extends through the at least one second microelectronic device opening;
wherein forming the first microelectronic device with the at least one bond pad in or on the first microelectronic device first surface comprises forming the first microelectronic device with a plurality of bond pads in or on the first microelectronic device first surface;
wherein forming the second microelectronic device with the at least one bond pad in or on the second microelectronic device first surface comprises forming the second microelectronic device with a plurality of bond pads in or on the second microelectronic device first surface, and wherein the opening through the second microelectronic device comprises a single opening;
and
wherein electrically attaching at least one bond wire to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device comprises electrically attaching a plurality of bond wires, wherein the plurality of bond wires extend through the single opening to form electrical connections between the plurality of bond pads in or on the first microelectronic device first surface and corresponding bond pads of the plurality bond pads in or on the second microelectronic device first surface.

5 more elements

An electronic system, comprising:

a board;
and
a microelectronic package attached to the board, wherein the microelectronic package includes:
a first microelectronic device having a first surface and an opposing second surface, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface;
a second microelectronic device having a first surface and an opposing second surface, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface, wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extending through the second microelectronic device from the second microelectronic device first surface to the second microelectronic device second surface;
and
at least one bond wire electrically attached to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein the bond wire extends through the at least one second microelectronic device opening;
wherein the at least one bond pad in or on the first microelectronic device first surface comprises a plurality of bond pads;
wherein the at least one bond pad of the second microelectronic device comprises a plurality of bond pads and wherein the opening through the second microelectronic device comprises a single opening;
and
wherein the at least one bond wire comprises a plurality of bond wires, wherein the plurality of bond wires extend through the single opening to form electrical connections between the plurality of bond pads in or on the first microelectronic device first surface and corresponding bond pads of the plurality bond pads in or on the second microelectronic device first surface.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/096,392Filed 31 May 2016
Published: US 2019/0139936 A19 May 2019
Granted: 8 Sep 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10W 90/00
Package configurations
H10D 62/117
Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies: shapes of semiconductor bodies
H10W 72/0198
Manufacture or treatment: batch processes
H10W 72/075
Connecting or disconnecting: of bond wires

Family

US 2019/0139936 A1Pre-grant publication · published 9 May 2019
US 10,770,429 B2This patent

From the US filing history. Foreign family members aren’t listed.

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