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US 10,770,411 B2Granted
Device comprising a stack of electronic chips
AssigneeSTMicroelectronics (Rousset) SAS
InventorsClement Champeix, Nicolas Borrel
Life of this patent
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Abstract
A method of protecting a first chip in a multi-chip stack includes determining an electrical characteristic of a conductive loop. The conductive loop extends over a top portion of the first chip. The conductive loop also extends through the first chip and within a top portion of a second chip. The top portion of the second chip is adjacent to a bottom portion of the first chip. The method further includes determining whether the electrical characteristic indicates that an attack is being made to determine contents or operation of the first chip.
Claims24
A method of protecting a first chip in a multi-chip stack, the method comprising:
- having the multi-chip stack comprising the first chip stacked on a second chip, the first chip comprising a first semiconductor substrate comprising first active devices at a first major surface and an opposite second major surface, the second chip comprising a second semiconductor substrate comprising second active devices at a first major surface and an opposite second major surface, the second major surface of the first semiconductor substrate facing the second semiconductor substrate;
- having a detection circuit disposed in the first chip;
- determining, at the detection circuit, an electrical characteristic of a conductive loop that extends over a top portion of the first chip, through the first chip and within a top portion of a second chip that is adjacent a bottom portion of the first chip, wherein the conductive loop comprises
- a first through via extending completely through the first semiconductor substrate and having a first end at the first major surface of the first semiconductor substrate and a second end at the second major surface of the first semiconductor substrate,
- a second through via extending completely through the first semiconductor substrate and having a first end at the first major surface of the first semiconductor substrate and a second end at the second major surface of the first semiconductor substrate,
- a first track disposed in the first chip, the first track connecting the first end of the first through via to the first end of the second through via, and
- a second track disposed in the second chip, the second track connecting the second end of the first through via to the second end of the second through via;
- and
- determining whether the electrical characteristic indicates that an attack is being made to determine contents or operation of the first chip.
6 more elements
A method of protecting a first chip in a multi-chip stack, the method comprising:
- having the multi-chip stack comprising the first chip stacked on a second chip;
- detecting a physical separation of the first chip from the second chip using a first detection circuit and in response to a first loop becoming an open electrical circuit, wherein
- the first chip comprising a first semiconductor substrate, the first semiconductor substrate comprising a first interconnection layer at a front side and a back side, the first interconnection layer comprising the first detection circuit,
- the second chip is stacked with the first chip and located on the back side of the first chip,
- the first loop comprises a first portion disposed in the first chip and a second portion disposed in the second chip, and
- the first loop is a closed electric circuit;
- and
- triggering implementation of countermeasures intended to stop an attack of the first chip in response to detecting the physical separation, wherein the countermeasures comprise destroying confidential data or stopping operation of circuits of the first chip.
5 more elements
A method of protecting a first chip in a multi-chip stack, the method comprising:
- detecting a physical separation of the first chip from a second chip using a detection circuit and in response to a first loop becoming an open electrical circuit;
- triggering, in response to detecting the physical separation, implementation of countermeasures intended to stop an attack of the first chip, wherein the countermeasures comprise destroying confidential data or stopping operation of circuits of the first chip;
- wherein the first chip comprises
- a front side and a back side,
- first and second connection pads on the back side of the first chip,
- a first through via completely extending from the front side of the first chip to the back side of the first chip, the first through via having a first end at the front side of the first chip and a second end at the back side of the first chip, wherein the first connection pad is connected to the first through via,
- a second through via completely extending from the front side of the first chip to the back side of the first chip, the second through via having a first end at the front side of the first chip and a second end at the back side of the first chip, wherein the second connection pad is connected to the second through via,
- a first track located at the front side of the first chip, the first track electrically connecting the first end of the first through via to the first end of the second through via, and
- the detection circuit located in the first chip and electrically coupled to the first track;
- and
- wherein the second chip is stacked with the first chip and located on the back side of the first chip, and wherein the second chip comprises
- third and fourth connection pads, wherein the first connection pad is soldered to the third connection pad, and wherein the second connection pad is soldered to the fourth connection pad, and
- a second track located at the second chip, the second track electrically connecting the second end of the first through via to the second end of the second through via.
10 more elements
Dependencies are inferred from the claim text.