US 10,770,404 B2Granted

Shielding for through-silicon-via noise coupling

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsJaw-Juinn Horng, Chung-Peng Hsieh

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Abstract

In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard ring is disposed in the semiconductor substrate and entirely surrounds the active area. The first guard ring has a first conductivity type. A via penetrates through the semiconductor substrate and is spaced apart from the active area such that the via is disposed outside of the first guard ring. A second guard ring is disposed in the semiconductor substrate and entirely surrounds the via and the first guard ring. The second guard ring has the first conductivity type and is disjoint from the first guard ring.

Claims20

Dependent claims

A method of shielding to prevent signals carried by a through substrate via from causing noise in an active area of an integrated circuit, comprising:

forming a first guard ring around a first area comprising the through substrate via, wherein the first guard ring has a first conductivity type;
and
forming a second guard ring around a second area comprising the active area, wherein the second guard ring has the first conductivity type;
wherein the through substrate via is outside of the second area fully surrounded by the second guard ring,
wherein the active area is outside of the first area fully surrounded by the first guard ring, and
wherein the active area is directly between a first portion of the second guard ring and a second portion of the second guard ring, wherein the first portion of the second guard ring is directly between the active area and the through substrate via, and wherein the first portion of the second guard ring has a first thickness greater than a second thickness of the second portion of the second guard ring.

3 more elements

An integrated circuit device, comprising:

a semiconductor body;
an active area disposed in the semiconductor body;
a via penetrating through the semiconductor body without passing through the active area;
a first contiguous region throughout which the semiconductor body is doped to at least a first concentration of a first doping type, the first contiguous region surrounding an area of the semiconductor body comprising the active area;
and
a second contiguous region throughout which the semiconductor body is doped to at least the first concentration of the first doping type, the second contiguous region surrounding the via, the second contiguous region being disjoint from the first contiguous region;
wherein the semiconductor body is not doped to the first doping type or is doped to a second concentration of the first doping type that is less than the first concentration;
wherein the via is outside the area surrounded by the first contiguous region;
and
wherein the via is directly between a first portion of the second contiguous region and a second portion of the second contiguous region, wherein the first portion of the second contiguous region is directly between the via and the active area, and wherein the first portion of the second contiguous region has a first thickness greater than a second thickness of the second portion of the second contiguous region.

7 more elements

An integrated circuit device, comprising:

a semiconductor body;
an active area disposed in the semiconductor body;
a via penetrating through the semiconductor body without passing through the active area;
a first contiguous region throughout which the semiconductor body is doped to at least a first concentration of a first doping type, the first contiguous region surrounding an area of the semiconductor body comprising the active area;
and
a second contiguous region throughout which the semiconductor body is doped to at least the first concentration of the first doping type, the second contiguous region surrounding the via, the second contiguous region being disjoint from the first contiguous region;
wherein the semiconductor body is not doped to the first doping type or is doped to a second concentration of the first doping type that is less than the first concentration;
wherein the via is outside the area surrounded by the first contiguous region;
and
wherein the active area is directly between a first portion of the first contiguous region and a second portion of the first contiguous region, wherein the first portion of the first contiguous region is directly between the active area and the via, and wherein the first portion of the first contiguous region has a first thickness greater than a second thickness of the second portion of the first contiguous region.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/220,236Filed 14 Dec 2018 · continuation
Priority: 12 Mar 2013
Published: US 2019/0122997 A125 Apr 2019
Granted: 8 Sep 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10W 42/20
Arrangements for protection of devices: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 20/217
Through-semiconductor vias, e.g. TSVs: comprising ring-shaped isolation structures outside of the via holes
H10W 20/43
Characterised by their conductive parts: layouts of interconnections

Family

Application13/795,035Parent of this continuation · filed 12 Mar 2013
Application14/944,907Parent of this continuation · filed 18 Nov 2015
US 9,219,038 B2Parent of this continuation · filed 22 Dec 2015
US 2019/0122997 A1Pre-grant publication · published 25 Apr 2019
US 10,163,809 B2Parent of this continuation
US 2014/0264772 A1Published application
US 2016/0071806 A1Published application
US 10,770,404 B2This patent

From the US filing history. Foreign family members aren’t listed.

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