Transistor with gate extension to limit second gate effect

A transistor, comprising:

• a semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region, the channel region having a source interface, a drain interface, and bounded by edges of the channel region extending from the source interface to the drain interface, wherein the edges of the channel region are on two boundaries between a field-sensitive semiconductor material and an isolation material;
• an insulator layer on the channel region;
• a gate on the insulator layer, the gate disposed over the channel region and extending entirely between the source region and the drain region, the gate having extensions beyond the edges of the channel region, the extensions configured to protect the edges of the channel region from electrical fields generated from a handle wafer;
• and
• a shielding means over the gate to protect the edges of the channel region from the electrical fields generated from the handle wafer.