Connected plane stiffener within integrated circuit chip carrier

A method of fabricating an integrated circuit (IC) chip carrier comprising a lower surface, an upper surface, and a center, the method comprising:

• forming a first plane fabrication layer upon a lower periphery layer, the lower periphery layer comprising the lower surface of the IC chip carrier;
• forming one or more first planes within the first plane fabrication layer;
• forming a plane separation layer upon the one or more first planes and upon the first plane fabrication layer;
• forming a plurality of channel vias within the plane separation layer and upon the one or more first planes, each channel via comprising a width, a length greater than the width, and a width bisector that is coincident with the center of the IC chip carrier;
• forming a second plane fabrication layer upon the plurality of channel vias and upon the plane separation layer;
• forming one or more second planes within the second plane fabrication layer and upon the plurality of channel vias;
• and
• forming an upper periphery layer upon the one or more second planes and upon the plane fabrication layer, the upper periphery layer comprising the upper surface of the IC chip carrier.