Printed circuit board having insulating metal oxide layer covering connection pad

A semiconductor package comprising:

• a base substrate layer;
• a first connection pad and a second connection pad disposed on a first surface and a second surface of the base substrate layer, respectively,
• wherein the first connection pad and the second connection pad each comprises a first metal and wherein the first connection pad includes a top surface and a plurality of side surfaces extending from the top surface to the first surface of the base substrate layer;
• a first pad cover layer covering the top surface of the first connection pad and comprising an insulating metal oxide having a second metal different from the first metal, wherein the first pad cover layer is absent from the plurality of side surfaces of the first connection pad;
• a semiconductor chip comprising a chip pad;
• and
• a bonding wire comprising a first end connected to the chip pad and a second end connected to the first connection pad through the first pad cover layer,
• wherein the bonding wire comprises a third metal different from the first metal;
• and
• a first intermetallic compound arranged between the second end of the bonding wire and the first connection pad, wherein the first intermetallic compound is a compound of the first metal and the third metal;
• and
• first fragments arranged at an interface between the second end of the bonding wire and the first intermetallic compound, wherein the first fragments comprise a same material as the first pad cover layer.

A semiconductor package comprising:

• a printed circuit board (PCB) comprising:
• a base substrate layer,
• a first connection pad and a second connection pad disposed on a first surface and a second surface of the base substrate layer, respectively, wherein the first connection pad includes a top surface and a plurality of side surfaces extending from the top surface to the first surface of the base substrate layer, and
• a first pad cover layer covering the top surface of the first connection pad, wherein the first pad cover layer is absent from the plurality of side surfaces of the first connection pad;
• and
• a semiconductor chip comprising a chip pad;
• a bonding wire comprising a first end connected to the chip pad and a second end connected to the first connection pad through the first pad cover layer, wherein the first pad cover layer has a thickness less than about 5.0 nm;
• a solder joint attached onto the second connection pad;
• a first intermetallic compound arranged between the second end of the bonding wire and the first connection pad;
• and
• fragments arranged at an interface between the second end of the bonding wire and the first intermetallic compound, wherein the fragments comprise a same material as the first pad cover layer.