Semiconductor device and method for manufacturing semiconductor device

A power module, comprising:

• a first semiconductor chip mounted on a first island part;
• a second semiconductor chip mounted on a second island part;
• a third semiconductor chip mounted on a third island part;
• a fourth semiconductor chip mounted on a forth island part;
• a fifth semiconductor chip mounted on the forth island part;
• a sixth semiconductor chip mounted on the forth island part;
• a first driving semiconductor chip mounted on a fifth island part and connected to each of the first to third semiconductor chips;
• a second driving semiconductor chip mounted on a sixth island part and connected to each of the fourth to sixth semiconductor chips;
• a first plurality of wires connecting the first driving semiconductor chip to the first, second and third semiconductor chips;
• a second plurality of wires connecting the second driving semiconductor chip to the fourth, fifth and sixth semiconductor chips;
• a first lead terminal connected to the first semiconductor chip by a first wire;
• a second lead terminal connected to the second semiconductor chip by a second wire;
• a third lead terminal connected to the third semiconductor chip by a third wire;
• a fourth lead terminal connected to the fourth semiconductor chip by a fourth wire and extending from the first island part;
• a fifth lead terminal connected to the fifth semiconductor chip by a fifth wire and extending from the second island part;
• a sixth lead terminal connected to the sixth semiconductor chip by a sixth wire and extending from the third island part;
• and
• a seventh lead terminal extending from the forth island part,
• wherein the first to sixth semiconductor chips are arranged in a first direction, the first driving semiconductor chip and the second driving semiconductor chip are arranged in the first direction, and the second driving semiconductor chip and the seventh lead terminal are arranged opposite to each other in a second direction across the fourth to sixth semiconductor chips, the second direction being perpendicular to the first direction,
• wherein the first to sixth wires are directly connected to the first to sixth lead terminals, respectively,
• the first to sixth wires are electrically connected only between the first to sixth lead terminals and the first to sixth semiconductor chips, respectively.