Integrated circuit and fabrication method thereof

A method for fabricating an integrated circuit, comprising:

• forming a first polish stop layer above a memory device;
• depositing a first inter-layer dielectric layer over the first polish stop layer, wherein the first inter-layer dielectric layer has a first portion over the first polish stop layer and a second portion that is not over the first polish stop layer;
• forming a second polish stop layer over the second portion of the first inter-layer dielectric layer, wherein the second polish stop layer is not over the first portion of the first inter-layer dielectric layer, wherein a bottom surface of the first polish stop layer is at least partially at a position higher than a top surface of a top electrode of the memory device after forming the second polish stop layer;
• and
• polishing the first inter-layer dielectric layer until reaching at least one of the first polish stop layer and the second polish stop layer.

An integrated circuit, comprising:

• a first inter-layer dielectric layer having a plurality of conductive features therein;
• a plurality of memory devices respectively over the conductive features, wherein each of the memory devices comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element;
• a second inter-layer dielectric layer, wherein the second inter-layer dielectric layer has a raised portion surrounding the memory devices and an extending portion extending from the raised portion, and the raised portion has a top surface higher than a top surface of the extending portion;
• and
• a polish stop layer having a first portion extending along the top surface of the extending portion and a second portion extending along a side surface of the raised portion, wherein a top surface of the first portion of the polish stop layer is lower than a top surface of the top electrodes of the memory devices.