Chamferless interconnect vias of semiconductor devices

A method of fabricating interconnects in a semiconductor device comprising:

• forming an interconnect layer comprising a conductive line;
• depositing a first aluminum-containing layer over the interconnect layer;
• depositing a first dielectric layer over the first aluminum-containing layer;
• depositing a second aluminum-containing layer over the first dielectric layer;
• depositing a second dielectric layer over the second aluminum-containing layer;
• forming a via opening having an upper portion in the second dielectric layer, exposing the second aluminum-containing layer;
• performing a first extension of the upper portion of the via opening through the exposed second aluminum-containing layer to expose the first dielectric layer;
• and
• performing a second extension of the upper portion of the via opening in the first dielectric layer to form a lower portion of the via opening, wherein a trench opening is concurrently formed in the second dielectric layer.

An interconnect structure in a semiconductor device comprising:

• a first interconnect layer comprising a first conductive line;
• a first aluminum-containing layer over the first interconnect layer;
• a second interconnect layer over the first aluminum-containing layer, wherein the second interconnect layer comprises a second aluminum-containing layer interposed within an interlayer dielectric layer;
• and
• an interconnect via connected to the first conductive line, wherein the interconnect via has chamferless sidewalls that partially expose the second aluminum-containing layer.