Methods and masks for line end formation for back end of line (BEOL) interconnects and structures resulting therefrom
AssigneeIntel Corporation
InventorsRichard E. Schenker, Charles H. Wallace
Life of this patent
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AssigneeIntel Corporation
InventorsRichard E. Schenker, Charles H. Wallace
Estimating the term…
Grating based plugs and cuts for feature end formation for back end of line (BEOL) interconnects are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a hardmask layer above an interlayer dielectric (ILD) material layer. A first patterned hardmask layer is formed above the hardmask layer. A second patterned hardmask layer is formed above the first patterned hardmask layer. A lithographic patterning mask is formed above the second patterned hardmask layer. Portions of the second patterned hardmask layer not protected by the regions of the lithographic patterning mask are removed to form a third patterned hardmask layer and then the lithographic patterning mask is removed. A combined pattern of the third patterned hardmask layer and the first patterned hardmask layer is transferred to the hardmask layer and to the ILD material layer.
A method of fabricating an interconnect structure for a semiconductor die, the method comprising:
A method of fabricating an interconnect structure for a semiconductor die, the method comprising:
Dependencies are inferred from the claim text.