High speed arc suppressor
AssigneeArc Suppression Technologies
InventorsReinhold Henke, Warren Kahle
Life of this patent
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Abstract
A high speed arc suppressor and method include a first phase-specific arc suppressor configured to suppress arcing across contacts of the power contactor in a positive domain and a second phase-specific arc suppressor configured to suppress arcing across the contacts in a negative domain. First and second high speed switches are configured to enable and disable operation of an associated one of the first and second phase-specific arc suppressors. First and second drivers are configured to drive the first and second high speed switches.
Claims12
A high speed arc suppressor configured to suppress arcing across a power contactor coupled to an alternating current (AC) power source, the high speed arc suppressor comprising:
- a first phase-specific arc suppressor configured to suppress arcing across contacts of the power contactor in a positive domain, comprising:
- a first high speed switch configured to enable or disable operation of the first phase-specific arc suppressor;
- and
- a first driver, coupled to the first high speed switch, configured to cause the first high speed switch to enable operation of the first phase-specific arc suppressor when an input signal from the contacts is in the positive domain and disable operation of the first phase-specific are suppressor when the input signal from the contacts is in a negative domain;
- and
- a second phase-specific arc suppressor configured to suppress arcing across the contacts in a negative domain, comprising:
- a second high speed switch configured to enable or disable operation of the second phase-specific arc suppressor;
- and
- a second driver, coupled to the second high speed switch, configured to cause the second high speed switch to enable operation of the first phase-specific arc suppressor when an input signal from the contacts is in the negative domain and disable operation of the first phase-specific arc suppressor when the input signal from the contacts is in the positive domain;
- wherein the first and second high speed switches are configured to switch the first and second phase-specific arc suppressors between the enable operation and the disable operation in not more than ten (10) microseconds;
- wherein the first and second high speed switches are insulated gate bipolar transistors (IGBT);
- and
- wherein each of the first and second phase-specific arc suppressors further comprises:
- an arc ignition detector circuit;
- a trigger lock circuit;
- and
- an arc burn memory.
A method of operation a high speed arc suppressor, comprising:
- enabling a first phase-specific arc suppressor of the high speed arc suppressor to suppress arcing across contacts of a power contactor when an alternating current (AC) signal from the power contactor is in a positive domain;
- disabling a second phase-specific arc suppressor of the high speed arc suppressor to suppress arcing across the contacts when the signal is in the positive domain;
- and
- upon the signal crossing into a negative domain:
- switching a first high speed switch of the first phase-specific arc suppressor to disable operation of the first phase-specific arc suppressor to suppress arcing across the contacts;
- and
- switching a second high speed switch of the first phase-specific arc suppressor configured to enable operation of the second phase-specific arc suppressor to suppress arcing across the contacts;
- wherein the first and second high speed switches are configured to switch the first and second phase-specific arc suppressors between the enable operation and the disable operation in not more than ten (10) microseconds;
- wherein the first phase-specific arc suppressor comprises a first driver and the second phase-specific arc suppressor comprises a second driver, and wherein switching the first and second high speed switches comprises driving the first and second high speed switches with the first and second drivers, respectively;
- wherein the first and second high speed switches are insulated gate bipolar transistors (IGBT);
- and
- wherein the each of the first and second phase-specific arc suppressors comprise a trigger lock configured to inhibit operation of an associated one of the first and second phase-specific arc suppressor for a predetermined time following an initial detection of an arc.
Dependencies are inferred from the claim text.