US 10,770,168 B2 · Memory sub-system with background scan and histogram statistics

Abstract

Several embodiments of systems incorporating memory sub-systems are disclosed herein. In one embodiment, a memory sub-system can include a memory component and a processing device configured to perform a background scan on a memory region of the memory component. In some embodiments, the background scan includes generating a bit error count (BEC) of a codeword saved on the memory region and saving statistical information corresponding to the BEC of the codeword to a histogram statistics log. In some embodiments, when the BEC of the codeword is greater than a BEC threshold, a refresh operation is scheduled for the memory region and/or logged. In these and other embodiments, when one or more error recovery error correction code (ECC) operations do not correct bit errors in the codeword, a refresh and/or retirement operation is schedule for the memory region and/or is logged.

Claims17

Dependent claims

A system, comprising:

a memory component comprising a plurality of memory regions configured to store a plurality of codewords;
and
a processing device operably connected to the memory component, wherein the processing device is configured to
generate a bit error count (BEC) of a first codeword of the plurality of codewords saved to a first memory region in the plurality of memory regions;
and
store statistical information corresponding to the BEC of the first codeword in a BEC histogram corresponding to the plurality of codewords, wherein storing the statistical information comprises incrementing a counter value of a bin of the BEC histogram corresponding to the BEC of the first codeword.

3 more elements

Dependencies are inferred from the claim text.

Memory sub-system with background scan and histogram statistics

Life of this patent

Memory sub-system with background scan and histogram statistics

Life of this patent

Abstract

Claims17