Memory device and operating method to determine a defective memory block

A memory device, comprising:

• one or more memory blocks;
• one or more peripheral circuits configured to perform an erase operation on a selected memory block and a threshold voltage distribution scan operation on one or more select transistors included in the selected memory block;
• and
• a control logic configured to control the one or more peripheral circuits and determine the selected memory block to be a normal memory block or a defective memory block based on a result of the threshold voltage distribution scan operation,
• wherein the control logic is configured to control the one or more peripheral circuits to perform the threshold voltage distribution scan operation after the erase operation of the selected memory block is completed, and
• wherein the one or more peripheral circuits are configured to scan threshold voltage distributions of the select transistors included in the selected memory block during the threshold voltage distribution scan operation, and detect whether scanned threshold voltage distributions fall within a normal range, or a left tail area or a right tail area falling out of the normal range.

A method of operating a memory device, comprising:

• performing an erase operation on a selected memory block;
• scanning threshold voltage distributions of one or more select transistors included in the selected memory block after the erase operation on the selected memory block is completed;
• and
• detecting whether scanned threshold voltage distributions of the select transistors of the selected memory block fall within a normal range, or a left tail area or a right tail area falling out of the normal range.