Shift register, driving circuit and display device

A driving circuit, comprising:

• N number of cascaded shift registers, where N is a positive integer greater than two,
• wherein a shift register of the N number of cascaded shift registers comprises:
• an output circuit, wherein the output circuit provides a signal at a first clock signal terminal to a gate signal output terminal under a control of a signal at a first node, or provides a signal at a first reference voltage terminal to the gate signal output terminal under a control of a signal at a second node;
• a node control circuit, wherein according to the signal at the first node or the signal at the second node, the node control circuit controls a level of the signal at the first node to be opposite to a level of the signal at the second node;
• a first node charging circuit, where the first node charging circuit includes a first control terminal, during a charging period of the first node in a non-scanning period, the first node charging circuit provides a signal at a first fixed voltage terminal to the first node under a control of a signal at the first control terminal;
• and
• a first control signal output circuit, wherein under a control of a signal at a second clock signal terminal, the first control signal output circuit transmits a signal at a third clock signal terminal to the first control terminal, and the first node charging circuit provides the signal at the first fixed voltage terminal to the first node.

A display device, comprising:

• a display region including a plurality of gate lines and a plurality of data line intersecting and insulated from the gate lines;
• and
• a non-display region including a driving circuit,
• wherein the driving circuit comprises:
• N number of cascaded shift registers, where N is a positive integer greater than two,
• wherein a shift register of the N number of cascaded shift registers comprises:
• an output circuit, wherein the output circuit provides a signal at a first clock signal terminal to a gate signal output terminal under a control of a signal at a first node, or provides a signal at a first reference voltage terminal to the gate signal output terminal under a control of a signal at a second node;
• a node control circuit, wherein according to the signal at the first node or the signal at the second node, the node control circuit controls a level of the signal at the first node to be opposite to a level of the signal at the second node;
• a first node charging circuit, where the first node charging circuit includes a first control terminal, during a charging period of the first node in a non-scanning period, the first node charging circuit provides a signal at a first fixed voltage terminal to the first node under a control of a signal at the first control terminal;
• and
• a first control signal output circuit, wherein under a control of a signal at a second clock signal terminal, the first control signal output circuit transmits a signal at a third clock signal terminal to the first control terminal, and the first node charging circuit provides the signal at the first fixed voltage terminal to the first node, and
• wherein the gate signal output terminal the shift register is electrically connected to a correspond gate line of the plurality of gate lines.