US 10,770,145 B2 · Two-part programming methods · patentgrep

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Abstract

Method of operating a memory include increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses, and subsequently increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses, wherein the first plurality of programming pulses have respective voltage levels within a first range of voltage levels, the second plurality of programming pulses have respective voltage levels within a second range of voltage levels, and a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.

Claims20

Dependent claims

A method of operating a memory, comprising:

increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses to control gates of the plurality of memory cells, wherein the first plurality of programming pulses each have a respective voltage level within a first range of voltage levels;
after applying the first plurality of programming pulses to the control gates of the plurality of memory cells, increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses to the control gates of the plurality of memory cells, wherein the second plurality of programming pulses each have a respective voltage level within a second range of voltage levels;
inhibiting the second subset of memory cells from programming for each programming pulse of the first plurality of programming pulses, and enabling the first subset of memory cells for programming for at least one programming pulse of the first plurality of programming pulses;
and
inhibiting the first subset of memory cells from programming for each programming pulse of the second plurality of programming pulses, and enabling the second subset of memory cells for programming for at least one programming pulse of the second plurality of programming pulses;
wherein a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.

3 more elements

A method of operating a memory, comprising:

increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses to control gates of the plurality of memory cells, wherein the first plurality of programming pulses each have a respective voltage level within a first range of voltage levels;
and
after applying the first plurality of programming pulses to the control gates of the plurality of memory cells, increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than a second voltage level that is lower than the particular voltage level in response to applying a second plurality of programming pulses to the control gates of the plurality of memory cells, wherein the second plurality of programming pulses each have a respective voltage level within a second range of voltage levels;
and
increasing respective threshold voltages of a third subset of memory cells of the plurality of memory cells to threshold voltage levels higher than the second voltage level and lower than the particular voltage level in response to at least one of applying the first plurality of programming pulses to the control gates of the plurality of memory cells and applying the second plurality of programming pulses to the control gates of tie plurality of memory cells;
wherein a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.

3 more elements

A method of operating a memory, comprising:

applying a first range of programming pulses to control gates of a plurality of memory cells such that respective threshold voltages of a first subset of memory cells of the plurality of memory cells are increased to be higher than or equal to a particular voltage level, wherein the first range of programming pulses comprises a first start voltage level and a first end voltage level higher than the first start voltage level;
after applying the first range of programming pulses to the control gates of the plurality of memory cells, applying a second range of programming pulses to the control gates of the plurality of memory cells such that respective threshold voltages of a second subset of memory cells of the plurality of memory cells are increased to be lower than the particular voltage level, wherein the second range of programming pulses comprises a second start voltage level and a second end voltage level higher than the second start voltage level;
inhibiting the second subset of memory cells from programming for each programming pulse of the first range of programming pulses, and enabling the first subset of memory cells for programming for at least one programming pulse of the first range of programming pulses;
and
inhibiting the first subset of memory cells from programming for each programming pulse of the second range of programming pulses, and enabling the second subset of memory cells for programming for at least one programming pulse of the second range of programming pulses;
wherein the first subset of memory cells and the second subset of memory cells are mutually exclusive;
and
wherein the first start voltage level is lower than or equal to the second end voltage level.

5 more elements

A method of operating a memory, comprising:

applying a first range of programming pulses to control gates of a plurality of memory cells such that respective threshold voltages of a first subset of memory cells of the plurality of memory cells are increased to be higher than or equal to a particular voltage level, wherein the first range of programming pulses comprises a first start voltage level and a first end voltage level higher than the first start voltage level;
after applying the first range of programming pulses to the control gates of the plurality of memory cells, applying a second range of programming pulses to the control gates of the plurality of memory cells such that respective threshold voltages of a second subset of memory cells of the plurality of memory cells are increased to be lower than a second threshold voltage level that is lower than the particular voltage level, wherein the second range of programming pulses comprises a second start voltage level and a second end voltage level higher than the second start voltage level;
inhibiting the second subset of memory cells from programming for each programming pulse of the first range of programming pulses, and enabling the first subset of memory cells for programming for at least one programming pulse of the first range of programming pulses;
and
inhibiting the first subset of memory cells from programming for each programming pulse of the second range of programming pulses, and enabling the second subset of memory cells for programming for at least one programming pulse of the second range of programming pulses;
wherein the first start voltage level is equal to the second end voltage level;
and
wherein at least one of applying the first range of programming pulses to the control gates of the plurality of memory cells and applying the second range of programming pulses to the control gates of the plurality of memory cells further causes respective threshold voltages of a third subset of memory cells of the plurality of memory cells to be increased to be higher than the second threshold voltage level and lower than the particular voltage level, wherein the first subset of memory cells, the second subset of memory cells and the third subset of memory cells are each mutually exclusive.

5 more elements

A method of operating a memory, comprising:

applying a first range of programming pulses to control gates of a plurality of memory cells such that respective threshold voltages of a first subset of memory cells of the plurality of memory cells are increased to be higher than or equal to a particular voltage level, wherein the first range of programming pulses comprises a first start voltage level and a first end voltage level higher than the first start voltage level;
after applying the first range of programming pulses to the control gates of the plurality of memory cells, applying a second range of programming pulses to the control gates of the plurality of memory cells such that respective threshold voltages of a second subset of memory cells of the plurality of memory cells are increased to be lower than a second threshold voltage level that is lower than the particular voltage level, wherein the second range of programming pulses comprises a second start voltage level and a second end voltage level higher than the second start voltage level;
inhibiting the second subset of memory cells from programming for each programming pulse of the first range of programming pulses, and enabling the first subset of memory cells for programming for at least one programming pulse of the first range of programming pulses;
and
inhibiting the first subset of memory cells from programming for each programming pulse of the second range of programming pulses, and enabling the second subset of memory cells for programming for at least one programming pulse of the second range of programming pulses;
wherein the first start voltage level is lower than the second end voltage level;
and
wherein at least one of applying the first range of programming pulses to the control gates of the plurality of memory cells and applying the second range of programming pulses to the control gates of the plurality of memory cells further causes respective threshold voltages of a third subset of memory cells of the plurality of memory cells to be increased to be higher than the second threshold voltage level and lower than the particular voltage level, wherein the first subset of memory cells, the second subset of memory cells and the third subset of memory cells are each mutually exclusive.

5 more elements

A memory device, comprising:

an array of memory cells comprising a plurality of memory cells;
and
control circuitry for control and/or access of the array of memory cells, wherein the control circuitry is configured to perform a method comprising:
increasing respective threshold voltages of a first subset of memory cells of the plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses to control gates of the plurality of memory cells, wherein the first plurality of programming pulses each have a respective voltage level within a first range of voltage levels;
and
after applying the first plurality of programming pulses to the control gates of the plurality of memory cells, increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than a second voltage level that is lower than the particular voltage level in response to applying a second plurality of programming pulses to the control gates of the plurality of memory cells, wherein the second plurality of programming pulses each have a respective voltage level within a second range of voltage levels;
inhibiting the second subset of memory cells from programming for each programming pulse of the first plurality of programming pulses, and enabling the first subset of memory cells for programming for at least one programming pulse of the first plurality of programming pulses;
inhibiting the first subset of memory cells from programming for each programming pulse of the second plurality of programming pulses, and enabling the second subset of memory cells for programming for at least one programming pulse of the second plurality of pros ramming pulses;
and
increasing respective threshold voltages of a third subset of memory cells of the plurality of memory cells to threshold voltage levels higher than the second voltage level and lower than the particular voltage level in response to at least one of applying the first plurality of programming pulses to the control gates of the plurality of memory cells and applying the second plurality of programming pulses to the control gates of the plurality of memory cells;
wherein the first subset of memory cells, the second subset of memory cells, and the third subset of memory cells are mutually exclusive;
and
wherein a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/298,313Filed 11 Mar 2019 · continuation
Priority: 20 Nov 2008
Published: US 2019/0206485 A14 Jul 2019
Granted: 8 Sep 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 16/0408
Using variable threshold transistors, e.g. FAMOS: comprising cells containing floating gate transistors
G11C 16/0458
Comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates:…

Family

Application12/274,727Parent of this continuation · filed 20 Nov 2008
Application13/334,339Parent of this continuation · filed 22 Dec 2011
US 8,089,805 B2Parent of this continuation · filed 3 Jan 2012
Application14/725,749Parent of this continuation · filed 29 May 2015
US 9,087,600 B2Parent of this continuation · filed 21 Jul 2015
Application15/287,956Parent of this division · filed 7 Oct 2016
US 9,502,101 B2Parent of this continuation · filed 22 Nov 2016
Application15/831,718Parent of this continuation · filed 5 Dec 2017
US 9,858,991 B2Parent of this division · filed 2 Jan 2018
US 2019/0206485 A1Pre-grant publication · published 4 Jul 2019
US 10,249,365 B2Parent of this continuation
Application15/831,718Parent of this division
Application15/287,956Parent of this continuation
US 2010/0124108 A1Published application
US 2012/0092932 A1Published application
US 2015/0262657 A1Published application
US 2017/0025170 A1Published application
US 2018/0096722 A1Published application
US 10,770,145 B2This patent

From the US filing history. Foreign family members aren’t listed.

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