Semiconductor memory devices including a memory array and related method incorporating different biasing schemes

A method of operating a semiconductor memory device, the method comprising:

• accessing at least one memory cell from a first set of memory cells located between a first row address line at a first voltage and a first set of column address lines during a first clock cycle;
• accessing at least one memory cell from a second set of memory cells located between the first set of column address lines and a second row address line at a second, different voltage during the first clock cycle;
• accessing at least one memory cell from a third set of memory cells located between the second row address line at the second, different voltage and a second set of column address lines during the first clock cycle;
• and
• accessing at least one memory cell from a fourth set of memory cells located between the second set of column address lines and a third row address line at the first voltage during the first clock cycle.