Variable resistance memory device and operating method thereof

A variable resistance memory device comprising:

• a variable resistance memory cell configured to store multi-bit data;
• a voltage generator configured to generate sequentially increased program voltage pulses, based on the multi-bit data;
• a program circuit configured to perform a program operation on the variable resistance memory cell by applying the program voltage pulses to the variable resistance memory cell, the programming operation being performed in a set operation and a reset operation, wherein the multi-bit variable resistance memory cell is programmed from a first resistance state to a second resistance state in the set operation and the multi-bit variable resistance memory cell is programmed from a third resistance state to a fourth resistance state in the reset operation, wherein a resistance of the first resistance state is higher than a resistance of the second resistance state while a resistance of the third resistance state is lower than a resistance of the fourth resistance state;
• and
• a read circuit configured to perform a verify read operation on the variable resistance memory cell,
• wherein a current-voltage curve of the variable resistance memory cell in the set operation includes a first region that does not exhibit a distinguishable hysteresis characteristic and a second region that exhibits both a hysteresis and a self-compliance characteristic, the current-voltage curve in the set operation in the second region being more gradual than the current-voltage curve in the set operation in the first region such that an increasement of a current per an increment of the applied program voltage pulses in the second region is greater than an increasement of a current per an increment of the applied program voltage pulses in the first region,
• wherein the program voltage pulses are applied to the variable resistance memory cell in the second region of the current-voltage curve of the variable resistance memory cell,
• wherein the read circuit is configured to determine the verify read operation as program pass when a read current of the variable resistance memory cell is larger than a minimum current limit and is smaller than a maximum current limit,
• wherein the variable resistance memory cell includes a variable resistance element and a first resistor coupled to the variable resistance element,
• wherein the self-compliance characteristic is generated by the variable resistance element and the first resistor.

A variable resistance memory device comprising:

• a variable resistance memory cell configured to store multi-bit data;
• a voltage generator configured to generate sequentially increased program voltage pulses, based on the multi-bit data;
• a program circuit configured to perform a program operation on the variable resistance memory cell by applying the program voltage pulses to the variable resistance memory cell, the programming operation being performed in a set operation and a reset operation, wherein the multi-bit variable resistance memory cell is programmed from a first resistance state to a second resistance state in the set operation and the multi-bit variable resistance memory cell is programmed from a third resistance state to a fourth resistance state in the reset operation, wherein a resistance of the first resistance state is higher than a resistance of the second resistance state while a resistance of the third resistance state is lower than a resistance of the fourth resistance state;
• and
• a read circuit configured to perform a verify read operation on the variable resistance memory cell,
• wherein a current-voltage curve of the variable resistance memory cell in the set operation includes a first region that does not exhibit a distinguishable hysteresis characteristic and a second region that exhibits both a hysteresis and a self-compliance characteristic, the current-voltage curve in the set operation in the second region being more gradual than the current-voltage curve in the set operation in the first region such that an increasement of a current per an increment of the applied program voltage pulses in the second region is greater than an increasement of a current per an increment of the applied program voltage pulses in the first region,
• wherein the program voltage pulses are applied to the variable resistance memory cell in the second region of the current-voltage curve of the variable resistance memory cell,
• wherein the read circuit is configured to determine the verify read operation as program pass when a read current of the variable resistance memory cell is larger than a minimum current limit and is smaller than a maximum current limit,
• wherein the variable resistance memory cell includes a variable resistance element and a first resistor or transistor coupled to the variable resistance element,
• wherein the self-compliance characteristic is generated by the variable resistance element and the first resistor or the transistor.