Method of operating resistive memory device reducing read disturbance

A method of operating a resistive memory device comprising a memory cell array including a plurality of resistive memory cells connected to a plurality of word lines in a first direction and a plurality of bit lines in a second direction substantially perpendicular to the first direction, the plurality of word lines including a first word line and a second word line relatively closer to a selection circuit than the first word line, and the plurality of bit lines including a first bit line and a second bit line relatively closer to the selection circuit than the first bit line, the method comprising:

• performing an access operation of selecting a memory cell from among the plurality of resistive memory cells;
• connecting the selected memory cell to a data line through the selection circuit, the selection circuit having selection transistors, each of the selection transistors being connected between a plurality of data lines and one of the plurality of word lines and the plurality of bit lines, the selection transistors being turned on in response to a column selection signal;
• determining a physical distance between the selection circuit and the selected memory cell;
• and
• differently applying a voltage level of the column selection signal to gates of the selection transistors based on the physical distance,
• wherein, when the selection transistors are connected between the plurality of data lines and the plurality of word lines, a first voltage level of the column selection signal when the selected memory cell is connected to the first word line is set to be higher than a second voltage level of the column selection signal when the selected memory cell is connected the second word line.

A resistive memory device, comprising:

• a memory cell array including a first resistive memory cell and a second resistive memory cell, the first resistive memory cell being connected between a first word line extending in a first direction and a first bit line extending in a second direction, and the second resistive memory cell being connected between a second word line extending in the first direction and a second bit line extending in the second direction;
• and
• a first row selection transistor configured to connect the first word line and a read circuit, a gate node of the first row selection transistor being connected to a row decoder;
• and
• a second row selection transistor configured to connect the second word line and the read circuit, a gate node of the second row selection transistor being connected to the row decoder,
• wherein the row decoder is configured to bias the gate node of the first row selection transistor to a first select voltage level from an unselect voltage level when the first resistive memory cell is selected, and to bias the gate node of the second row selection transistor to a second select voltage level from the unselect voltage level when the second resistive memory cell is selected, and
• the first select voltage level and the second select voltage level are different from each other.