Resistive memory device including compensation circuit

A resistive memory device, comprising:

• a memory cell array comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells;
• a control logic circuit that outputs a row address for the plurality of word lines, based on an address received from an external device;
• and
• a compensation circuit comprising a sampling circuit that generates a sampling value by sensing a leakage current that is applied to bit lines connected to selected memory cells on which memory operations are performed, from among the plurality of memory cells, a holding circuit that holds the sampling value and compensates, based on the sampling value, for voltages that are applied to the bit lines connected to the selected memory cells, and a switch having an end connected to the sampling circuit and another end connected to the holding circuit.

A resistive memory device, comprising:

• a memory cell array comprising a plurality of memory cells arranged in rows and columns;
• bit lines comprising a plurality of local bit lines respectively connected to the plurality of memory cells and a plurality of global bit lines connected to at least one of the plurality of local bit lines via a local-selected transistor;
• and
• a compensation circuit comprising a sampling circuit that generates a sampling value by sensing a leakage current that is applied to bit lines connected to selected memory cells on which memory operations are performed, and a holding circuit that compensates for a voltage applied to the bit lines that are connected to the selected memory cells, based on the sampling value.