SRAM based authentication circuit

A memory device, comprising:

• a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state;
• a physically unclonable function (PUF) generator, comprising:
• a first sense amplifier, coupled to first and second memory cells of the plurality of memory cells, and
• a second sense amplifier, also coupled to the first and second memory cells of the plurality of memory cells, wherein the first and second memory cells are located in first and second columns of the memory cell array, respectively;
• and
• a pre-charge/pre-discharge (PC/PD) circuit that is coupled to the plurality of memory cells, wherein the PC/PD circuit is configured to pre-charge bit lines of the first and second columns to either a positive supply voltage or to ground based on a data state of the plurality of memory cells before the first and second memory cells are accessed.

A memory device, comprising:

• a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state;
• a physically unclonable function (PUF) generator, coupled to the plurality of memory cells, that comprises:
• a first sense amplifier, and
• a column decoder, coupled between the plurality of memory cells and the first sense amplifier, that comprises at least four switches wherein each of the switches is coupled to one of four columns of the memory cell array, wherein while the data states of the plurality of memory cells are being read, the column decoder is configured to assert two of the four switches so as to allow the first sense amplifier to compare either respective discharging rates or respective charging rates of first and second memory cells of the plurality of memory cells that are coupled to the first sense amplifier through the asserted switches, and based on a voltage difference according to the comparison, provide an output signal for generating a PUF signature, wherein the first and second memory cells are located in first and second columns of the memory cell array, respectively;
• and
• a pre-charge/pre-discharge (PC/PD) circuit that is coupled to the plurality of memory cells, wherein the PC/PD circuit is configured to pre-charge bit lines of the first and second columns to either a positive supply voltage or to ground based on the data state of the plurality of memory cells before the first and second memory cells are accessed.