Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits

A processing array device, comprising:

• a plurality of memory cells arranged in an array having a plurality of columns and a plurality of rows, each memory cell having a storage element wherein the array has a plurality of sections and each section has a plurality of bit line sections and a plurality of bit lines with one bit line per bit line section, wherein the memory cells in each bit line section are all connected to a single read bit line and the plurality of bit lines in each section are distinct from the plurality of bit lines included in the other sections of the array;
• and
• wherein each bit line section further comprises a write inhibit circuitry that inhibits a write operation to the memory cells of the bit line section on a per write operation basis, a pullup element connected to the read bit line to pre-charge the read bit line to a logic “1”, and a pre-charge inhibit circuitry that inhibits the pre-charge of the read bit line for a period of time.