SRAM with burst mode address comparator

A burst-mode method for a memory, comprising:

• pre-charging a sense amplifier in a first read cycle:
• latching a bit decision in the sense amplifier after the pre-charging in the first read cycle;
• in a second read cycle following the first read cycle, asserting a burst mode signal for a portion of the second read cycle responsive to a row address for the second read cycle equaling a row address for the first read cycle;
• transferring the bit decision latched in the sense amplifier to a data output latch without pre-charging the sense amplifier during the second read cycle responsive to the assertion of the burst mode signal.

A memory, comprising:

• a word line;
• a plurality of columns, each column in the plurality of columns including a bitcell at an intersection of the column with the word line, a sense amplifier, and a bit line coupled to a sense node for the sense amplifier through a charge-transfer transistor;
• a burst mode address comparator configured to determine for a series of read cycles whether each read cycle is a burst mode read cycle or a normal read cycle;
• a bit line pre-charge circuit configured to pre-charge the bit line in each column in each natural read cycle, wherein the bit line pre-charge circuit is further configured to not pre-charge the bit line in each column in each burst mode read cycle.