SRAM cell for interleaved wordline scheme

A static random access memory (SRAM) cell laid out on a semiconductor substrate according to an SRAM cell layout, the SRAM cell layout comprising:

• upper and lower cell edges and left and right cell edges corresponding to an outer perimeter of the SRAM cell on the semiconductor substrate;
• a first power rail extending in parallel with and lying along the left cell edge or the right cell edge, wherein the first power rail is configured to couple the SRAM cell to a first voltage;
• and
• a second power rail extending in parallel with the first power rail and along a midline of the SRAM cell between the left and right cell edges, wherein the second power rail is configured to couple the SRAM cell to a second voltage, the second voltage differing from the first voltage;
• two wordlines extending in parallel with the upper and lower cell edges from the midline to a left or right cell edge of the SRAM cell and extending perpendicular to the first and second power rails;
• a local interconnect line extending in parallel with the two wordlines and spaced between nearest neighboring sidewalls of the two wordlines;
• and
• wherein the SRAM cell layout consists of three transistors between the midline of the SRAM cell and the left cell edge.

A static random access memory (SRAM) cell laid out on a semiconductor substrate according to an SRAM cell layout, the SRAM cell layout comprising:

• upper and lower cell edges and left and right cell edges corresponding to an outer perimeter of the SRAM cell on the semiconductor substrate;
• a first power rail extending in parallel with and lying along the left cell edge or the right cell edge, wherein the first power rail is configured to couple the SRAM cell to a first voltage;
• a second power rail extending in parallel with the first power rail and along a midline of the SRAM cell between the left and right cell edges, wherein the second power rail is configured to couple the SRAM cell to a second voltage, the second voltage differing from the first voltage;
• and
• two wordlines extending in parallel with the upper and lower cell edges over the SRAM cell and extending perpendicular to the first and second power rails;
• and
• a first local interconnect line extending in parallel with the two wordlines and spaced between nearest neighboring sidewalls of the two wordlines, wherein the SRAM cell layout consists of six transistors within the outer perimeter of the SRAM cell.